Printed Assemblies of Ultrathin, Microscale Inorganic Light Emitting Diodes for Deformable and Semitransparent Displays

ABSTRACT

Described herein are printable structures and methods for making, assembling and arranging electronic devices. A number of the methods described herein are useful for assembling electronic devices where one or more device components are embedded in a polymer which is patterned during the embedding process with trenches for electrical interconnects between device components. Some methods described herein are useful for assembling electronic devices by printing methods, such as by dry transfer contact printing methods. Also described herein are GaN light emitting diodes and methods for making and arranging GaN light emitting diodes, for example for display or lighting systems.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.12/778,588, filed on May 12, 2010, which claims the benefit of andpriority to U.S. Provisional Applications 61/177,458 filed on May 12,2009 and 61/241,465 filed on Sep. 11, 2009, all of which are herebyincorporated by reference in their entireties.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

This invention was made with United States governmental support underAward Nos. DE-FG02-07ER46471 and DE-FG02-07ER46453 awarded by the U.S.Department of Energy and Award No. DMI-0328162 awarded by the NationalScience Foundation. The U.S. government has certain rights in theinvention.

BACKGROUND OF INVENTION

This invention is in the field of printable electronics. This inventionrelates generally to methods for making and assembling electronicdevices and printable electronic devices.

A variety of platforms are available for printing structures on devicesubstrates and device components supported by device substrates,including nanostructures, microstructures, flexible electronics, and avariety of other patterned structures. For example, a number of patentsand patent applications describe different methods and systems formaking and printing a wide range of structures, including U.S. Pat. Nos.7,195,733, 7,557,367, 7,622,367 and 7,521,292, U.S. Patent ApplicationPublication Nos. 2009/0199960, 2007/0032089, 2008/0108171, 2008/0157235,2010/0059863, 2010/0052112 and 2010/0002402, and U.S. patent applicationSer. No. 11/145,574 (filed Jun. 2, 2005) and Ser. No. 11/981,380 (filedOct. 31, 2007); all of which are hereby incorporated by reference intheir entireties to the extent not inconsistent herewith.

SUMMARY OF THE INVENTION

Provided herein are methods for making electronic devices includingflexible devices and arrays of light emitting diodes (LEDs). Methods arealso provided for assembling electronic devices including simultaneouslyembedding device components into a polymer and molding of the polymerwith recessed features.

In one aspect, provided herein are methods for making electronicdevices. A method of this aspect comprises the steps of: providing agrowth substrate having a receiving surface; forming a semiconductorepilayer on the receiving surface via epitaxial growth; thesemiconductor epilayer having a first contact surface; bonding the firstcontact surface of the semiconductor epilayer to a handle substrate;releasing the semiconductor epilayer from the growth substrate whereinthe semiconductor epilayer remains bonded to the handle substrate,thereby exposing a second contact surface of the semiconductor epilayer;patterning the second contact surface of the semiconductor epilayer witha mask, thereby generating exposed regions and one or more maskedregions of the second contact surface; removing semiconductor materialfrom the exposed regions by etching the exposed regions, therebygenerating one or more semiconductor structures supported by the handlesubstrate; at least partially releasing the one or more semiconductorstructures from the handle substrate; and transferring at least one ofthe one or more semiconductor structures from the handle substrate to adevice substrate via dry transfer contact printing, thereby assemblingthe semiconductor structures on the device substrate to make theelectronic device.

For certain embodiments, the growth substrate is lattice matched to thesemiconductor epilayer, for example to within ±3.4% or ±1.9%. In certainembodiments, the growth substrate is lattice matched to thesemiconductor epilayer to within ±13.8%. Lattice matched growthsubstrate and epilayers are useful, for example, for growing highquality single crystalline layers via epitaxial growth. In embodiments,useful semiconductor epilayers include, but are not limited to a GaNlayer, an InGaN layer, a GaAsN layer, an AlGaN layer, an AlGaAsN layer,a GaAs layer, an InGaAs layer, an AlGaAs layer, an AlGaAsP layer, aGaAsSbN layer and an InN layer. Useful growth substrates include, butare not limited to, sapphire, silicon having a (111) orientation, SiC,ZnO, Si(100), MGAl₂O₄ (100), MgAl₂O₄ (111), A-plane sapphire, M-planesapphire, AlN, MnO, ZrB₂, LiGaO₂, (La,Sr)(Al,Ta)O₃, LaAlO₃, LaTaO₃,SrAlO₃ SrTaO₃, LiAlO₂, GaAs and InP.

Useful semiconductor epilayers include those having thicknesses selectedfrom the range of 5 nm to 20 μm or 1 μm to 5 μm. In some embodiments,the semiconductor epilayer is a multilayer. Useful multilayers includethose comprising layers of semiconductors having different compositions,different doping levels, different dopants or any combination of these.In one embodiment of this aspect, a multilayer comprises at least onep-type semiconductor layer in electrical communication with at least onen-type semiconductor layer. In one embodiment, the multilayer comprisesa plurality of light emitting diode (LED) device layers. Useful LEDdevice layers include contact layers, spreader layers, cladding layersand barrier layers.

In one embodiment, the semiconductor epilayer comprises GaN andoptionally a GaN multilayer. Useful GaN layers include those havingdifferent doping levels, different dopants, different thicknesses orboth. For example, in one embodiment, a GaN multilayer comprises atleast one p-type GaN layer in electrical communication with at least onen-type GaN layer. In an embodiment, a GaN multilayer comprises materialincluding GaN, InGaN, AlGaN, GaN:Mg, GaN:Si, GaN:AlN, GaN:ZnO or anycombination of these.

In a specific embodiment, the handle substrate comprises silicon and thestep of bonding the first contact surface of the semiconductor epilayerto the handle substrate comprises contacting the first contact surfaceto an external surface of the handle substrate so as to establish Vander Waals bonding between the semiconductor epilayer and the handlesubstrate. Useful handle substrates include those comprising an adhesionlayer. Useful adhesion layers include, but are not limited to, thosecomprising Au, Al, Pd, In, Ni and polymers such as polyurethanes,photoresists, polyimide, silicones and any combination of these.

In certain embodiments, a sacrificial layer is provided between thegrowth substrate and the semiconductor epilayer. For these embodiments,the step of partially releasing the semiconductor epilayer optionallycomprises at least partially removing the sacrificial layer, for exampleby etching or dissolving the sacrificial layer. Useful etching processesinclude electrochemical and photoelectrochemical etching processes.Useful sacrificial layers include, but are not limited to InGaN, SiO₂,AlAs, Si₃N₄, ZnO, AlN, HfN, AlInN and any combination of these.

In one embodiment, the semiconductor epilayer and the growth substratemeet at an interface and the step of releasing the semiconductor layerfrom the growth substrate comprises exposing the interface toelectromagnetic radiation. In an embodiment, the electromagneticradiation is passed through the growth substrate. Optionally, theelectromagnetic radiation comprises laser radiation. Usefulelectromagnetic radiation comprises electromagnetic radiation having awavelength selected over the range of 100 to 800 nm, a fluence selectedover the range of 400 to 600 mJ/cm² and any combination thereof.Specific examples of electromagnetic radiation include, but are notlimited to: KrF pulsed excimer laser at 248 nm, 38 ns pulse time at 600mJ/cm², for epilayers grown on sapphire; third harmonic of pulsedQ-switched Nd:YAG laser at 355 nm, 5 ns pulse time at 400 mJ/cm², forepilayers grown on sapphire; pulsed second harmonic Nd:YAG at 532 nm, 10ns pulse time at energy greater than 12mJ/cm², for epilayers grown onsapphire. In a further embodiment of this aspect, an absorbing layer isprovided at the interface between the growth substrate and thesemiconductor epilayer and the electromagnetic radiation is at leastpartially absorbed by the absorbing layer to release the semiconductorepilayer.

In one embodiment, the mask provided on the second contact surface ofthe epilayer includes a first mask layer comprising Si₃N₄. Optionallythe mask includes a second mask comprising a metal provided over thefirst mask layer. Useful mask layers further include those comprising adielectric, such as Si₃N₄ and SiO₂; a metal, such as Al, Au and Cu; andany combination of these.

In embodiments, the step of removing material from exposed regions ofthe masked semiconductor epilayer comprises etching the exposed regions.Useful etching processes include reactive ion etching, deep reactive ionetching and inductive coupled plasma reactive ion etching. In someembodiments, removing material from exposed regions of the maskedsemiconductor epilayer exposes side-walls of the remaining semiconductorstructure. In certain embodiments, an etch block layer, a mask layer orboth is deposited on at least a portion of the exposed side-walls, forexample to protect the side walls from being etched during a subsequentreleasing step.

In some embodiments, partially releasing semiconductor epilayers from ahandle substrate results in semiconductor structures anchored to thehandle substrate, for example by at least one homogenous anchor or atleast one heterogeneous anchor. In other embodiments, one method furthercomprises a step of anchoring a semiconductor structure to handlesubstrate, for example by at least one homogeneous anchor or at leastone heterogeneous anchor.

In embodiments, the step of transferring comprises a dry transfercontact printing method, for example as known in the art. A specific drytransfer contact printing technique useful for the methods describedherein comprises transferring at least one semiconductor structure froma handle substrate to a device substrate via contact printing using aconformal transfer device, such as a PDMS stamp.

Useful device substrates include, but are not limited to, glasssubstrates, polymer substrates, flexible substrates, large areasubstrates, pre-metalized substrates, substrates pre-patterned with oneor more device components, and any combination of these.

Another method of this aspect comprises the steps of: providing a growthsubstrate having a receiving surface; forming a semiconductor epilayeron the receiving surface via epitaxial growth; said semiconductorepilayer having a first contact surface; bonding the first contactsurface of the semiconductor epilayer to a handle substrate; releasingthe semiconductor epilayer from the growth substrate, wherein at least aportion of the semiconductor epilayer remains bonded to the handlesubstrate, thereby exposing a second contact surface of thesemiconductor epilayer; processing the semiconductor epilayer on thehandle substrate, thereby generating one or more semiconductorstructures supported by said handle substrate; transferring at least oneof the one or more semiconductor structures from the handle substrate toa device substrate via dry transfer contact printing, thereby assemblingsaid semiconductor structures on said device substrate to make saidelectronic device.

Another method of this aspect comprises the steps of: providing a firstgrowth substrate having a first receiving surface; forming a firstsemiconductor epilayer on the first receiving surface via epitaxialgrowth; the first semiconductor epilayer having a first contact surface;bonding the first contact surface of the first semiconductor epilayer toa handle substrate; releasing the first semiconductor epilayer from thefirst growth substrate, wherein at least a portion of the firstsemiconductor epilayer remains bonded to the handle substrate, therebyexposing a second contact surface of the first semiconductor epilayer;providing a second growth substrate having a second receiving surface;forming a second semiconductor epilayer on the second receiving surfacevia epitaxial growth; the second semiconductor epilayer having a thirdcontact surface; bonding the third contact surface of the secondsemiconductor epilayer to the handle substrate, the first semiconductorepilayer or both; releasing the second semiconductor epilayer from thesecond growth substrate, the first semiconductor epilayer or both,wherein at least a portion of the second semiconductor epilayer remainsbonded to the handle substrate, the first semiconductor epilayer orboth, thereby exposing a fourth contact surface of the secondsemiconductor epilayer; processing the first semiconductor epilayer, thesecond semiconductor epilayer or both the first and the secondsemiconductor epilayers on the handle substrate, thereby generating oneor more semiconductor structures supported by the handle substrate;transferring at least one of the one or more semiconductor structuresfrom the handle substrate to a device substrate via dry transfer contactprinting, thereby assembling the semiconductor structures on the devicesubstrate to make the electronic device. In a specific embodiment, thestep of bonding the third contact surface of the second semiconductorepilayer to the handle substrate, the first semiconductor epilayer orboth comprises bonding at least a portion of the third contact surfaceof the second semiconductor epilayer to the second contact surface ofthe first semiconductor epilayer.

Certain embodiments further comprise a step of processing asemiconductor epilayer on a growth substrate, for example processing afirst semiconductor epilayer on a first growth substrate, a secondsemiconductor epilayer on a second growth substrate or processing both afirst semiconductor epilayer on a first growth substrate and a secondsemiconductor epilayer on a second growth substrate. In embodiments, thestep of processing a semiconductor epilayer on a handle substrate or agrowth substrate comprises a processing method including, but notlimited to, a patterning process, a lithography process, a growthprocess, a polishing process, a deposition process, an implantationprocess, an etching process, an annealing process, a molding process, acuring process, a coating process, exposure to electromagnetic radiationor any combination of these. In specific embodiments, the step ofprocessing a semiconductor epilayer on a handle substrate comprisesforming one or more ohmic contacts on a semiconductor epilayer, formingone or more thermal management structures on a semiconductor epilayer orforming one or more ohmic contacts and forming one or more thermalmanagement structures.

In certain embodiments, the handle substrate comprises a materialincluding, but not limited to: a doped or undoped semiconductor; asingle crystal material; a polycrystalline material; a ceramic such asSiC, Si₃N₄, fused silica, alumina (Al₂O₃), ZrO₂, MgO, pyrolytic Boronnitride (PBN), aluminum nitride, aluminum silicate and titania; apolymer; glass; quartz; a semiconductor with or without a thermal oxidelayer; and any combination of these. Useful handle substrates alsoinclude substrates having an adlayer or substrates coated by ordeposited with a film of any of the above materials or other materialsincluding but not limited to a polymer, a sol-gel, a polymer precursor,an incompletely cured sol-gel. Use of certain materials for the handlesubstrate can be advantageous as subsequent processing of devices ordevice components on the handle substrate can also cure, anneal orotherwise process the materials of or coated on the handle wafer. Forexample when the processing includes a high temperature step a handlesubstrate including a film comprising a thermally curable polymer or anuncured or incompletely cured sol-gel can be cured. In certainembodiments, the composition of a handle substrate is driven by therequirements for subsequent processing of device elements on the handlesubstrate. For example, in embodiments when processing on the handlesubstrate includes high temperature processing (e.g., annealing or ohmiccontact formation processes), the handle substrate is selected so as tobe compatible with the associated high temperatures (e.g., ceramics,semiconductors). In embodiments when processing on the handle substrateincludes exposure to reactive chemicals (e.g., acids, bases, chemicaletchants), the handle substrate is selected so as to be compatible withthe exposure conditions (e.g., chemically inert).

Methods of this aspect are useful, for example for making an array ofLEDs. A specific method for making an array of LEDs comprises the stepsof: providing a sapphire growth substrate having a receiving surface;forming a GaN epilayer on the receiving surface via epitaxial growth;wherein the GaN epilayer is a multilayer comprises at least one p-typeGaN semiconductor layer in electrical communication with at least onen-type GaN semiconductor layer; the GaN multilayer having a firstcontact surface; bonding the first contact surface of the GaN multilayerto a handle substrate; releasing the GaN multilayer from the sapphiregrowth substrate wherein the GaN multilayer remains bonded to the handlesubstrate, thereby exposing a second contact surface of the GaNmultilayer; patterning the second contact surface of the GaN multilayerwith a mask, thereby generating exposed regions and one or more maskedregions of the second contact surface; removing material from theexposed regions by etching the exposed regions, thereby generating oneor more LED device structures supported by the handle substrate; atleast partially releasing the one or more LED device structures from thehandle substrate; and transferring at least a portion of the one or moreLED device structures from the handle substrate to a device substratevia dry transfer contact printing, thereby making an array of LEDs.

Another specific method for making an array of LEDs comprises the stepsof: providing a silicon growth substrate having a (111) orientation andhaving a receiving surface; generating a GaN multilayer on the receivingsurface of the growth substrate via epitaxial growth; the GaN multilayercomprising at least one p-type GaN layer in electrical contact with atleast one p-type GaN layer; the GaN multilayer having a contact surface;patterning the contact surface of the GaN multilayer with a mask,thereby generating exposed regions and one or more masked regions of theGaN multilayer; removing material from the exposed regions by etchingthe exposed regions and into the silicon growth substrate, therebyexposing a portion of the silicon growth substrate and generating one ormore LED device structures; at least partially releasing the one or moreLED device structures from the growth substrate by anisotropic etchingthe exposed portion of the silicon growth substrate; and transferring atleast a portion of the one or more LED device structures from thesilicon growth substrate to a device substrate via dry transfer contactprinting, thereby making the array of LEDs.

For certain embodiments of methods for making an array of LEDs, the stepof removing material etches a depth into the growth or host substrategreater than or equal to 5 nm, or selected over the range of 5 nm to 10μm. In embodiments, anisotropic etching of a silicon (111) substrateoccurs preferentially along <110> directions. Useful anisotropic etchingmethods include directional wet etching using an anisotropic etchantsuch as KOH or tetramethylammonium hydroxide (TMAH).

Another specific method for making an array of LEDs comprises the stepsof: providing a sapphire growth substrate having a receiving surface;providing a sacrificial layer on the receiving surface of the sapphiregrowth substrate; generating a GaN multilayer on the sacrificial layervia epitaxial growth; the GaN multilayer comprising at least one p-typeGaN layer in electrical contact with at least one n-type GaN layer; theGaN multilayer having a contact surface; patterning the contact surfaceof the GaN multilayer with a mask, thereby generating exposed regionsand one or more masked regions of the GaN multilayer; removing materialfrom the exposed regions by etching the exposed regions, therebyexposing a portion of the sacrificial layer and generating one or moreLED device structures; at least partially releasing the one or more LEDdevice structures from the growth substrate by removing at least aportion of the sacrificial layer using directional etching,electrochemical etching or photoelectrochemical etching; andtransferring at least a portion of the one or more LED device structuresfrom the sapphire growth substrate to a device substrate via drytransfer contact printing, thereby making the array of LEDs.

Useful sacrificial layers include InGaN, SiO₂, AlAs, Si₃N₄, ZnO, AlN,HfN, AIInN and any combination of these. In some embodiments, a bufferlayer or an etch block layer is provided between the growth substrateand the sacrificial layer, for example a buffer layer or an etch blocklayer comprising GaN. Buffer layers and etch block layers are useful,for example, to prevent etching of a GaN device layer during asubsequent etching or releasing step.

In a specific embodiment, a method of this aspect comprises the stepsof: providing a sapphire growth substrate having a receiving surface;providing a sacrificial layer on the receiving surface of said sapphiregrowth substrate; providing an etch block layer on the sacrificiallayer, for example via epitaxial growth; generating a GaN multilayer onthe etch block layer via epitaxial growth; patterning the contactsurface of the GaN multilayer with a mask, thereby generating exposedregions and one or more masked regions of the GaN multilayer; removingmaterial from the exposed regions by etching the exposed regions,thereby exposing a portion of the sacrificial layer and generating oneor more LED device structures; at least partially releasing said one ormore LED device structures from said growth substrate by removing atleast a portion of the sacrificial layer using directional etching,electrochemical etching or photoelectrochemical etching; andtransferring at least a portion of the one or more LED device structuresfrom the sapphire growth substrate to a device substrate via drytransfer contact printing. In an embodiment, a method of this aspectfurther comprises generating an etch block layer in at least a portionof the exposed regions, for example to prevent further etching of saidexposed regions during the step of at least partially releasing.

In some embodiments, a sacrificial layer is removed during the releasingstep by exposing the sacrificial layer to a selective etchant, forexample HCl, HF, H₃PO₄, KOH, NH₄Cl, chelating amines, 1,2-diaminoethane(DAE), NaOH and any combination of these. For specific embodiments, thereleasing step comprises exposing the sacrificial layer toelectromagnetic radiation, for example electromagnetic radiation havingwavelengths selected over the range of 100 nm to 800 nm orelectromagnetic radiation from a xenon lamp. In one embodiment, theelectromagnetic radiation is first passed through an undoped GaN filmbefore exposing the sacrificial layer, for example to optically filterthe electromagnetic radiation to remove at least a portion of theelectromagnetic radiation absorbed by the undoped GaN film. For someembodiments, the releasing step comprises providing the sacrificiallayer at an electric potential, for example an electric potential 600 mVto 800 mV greater than the potential of a buffer layer, the growthsubstrate or an etching solution. For some embodiments, the sacrificiallayer is simultaneously exposed to an etching solution while it is heldat a potential different from the etching solution. For someembodiments, the sacrificial layer is simultaneously exposed to anetching solution while it is held at a potential different from theetching solution and being exposed to electromagnetic radiation. In aspecific embodiment, the GaN multilayer is grown on a sacrificial layercomprising ZnO and the step of at least partially releasing comprisesetching the sacrificial layer with NH₄Cl etchant.

Another specific method for making an array of LEDs comprises the stepsof: providing a sapphire growth substrate having a receiving surface;generating a GaN multilayer on the sapphire growth substrate viaepitaxial growth; the GaN multilayer comprising at least one p-type GaNlayer in electrical contact with at least one n-type GaN layer; the GaNmultilayer having a first contact surface, wherein the GaN multilayerand the sapphire growth substrate meet at an interface; bonding thefirst contact surface of the GaN multilayer to a handle substrate;exposing the interface between the GaN multilayer and the sapphiregrowth substrate to electromagnetic radiation; releasing the GaNmultilayer from the sapphire growth substrate wherein the GaN multilayerremains bonded to the handle substrate, thereby exposing a secondcontact surface of the GaN multilayer; patterning the second contactsurface of the GaN multilayer with a mask, thereby generating exposedregions and one or more masked regions of the GaN multilayer; removingmaterial from the exposed regions by etching the exposed region, therebygenerating one or more LED device structures; at least partiallyreleasing the one or more LED device structures from the handlesubstrate; and transferring at least a portion of the one or more LEDdevice structures from the handle substrate to a device substrate viadry transfer contact printing, thereby making the array of LEDs.

In a specific embodiment, the interface is exposed to electromagneticradiation, optionally laser radiation. Optionally, the electromagneticradiation is passed through the sapphire growth substrate. In oneembodiment, the handle substrate comprises an external metal film andthe first contact surface of the GaN multilayer is bonded to the handlesubstrate when it is contacted to the external metal film. Inembodiments where there is an external metal film and the interface isexposed to electromagnetic radiation, the external metal film optionallyreflects at least a portion of the electromagnetic radiation, therebyexposing the interface to electromagnetic radiation.

In an exemplary embodiment for making an array of LEDs, the GaNmultilayer comprises at least one p-type GaN layer, at least one n-typeGaN layer and a quantum well region comprising InGaN positioned betweenthe p-type GaN layer and the n-type GaN layer. Specific methods of thisaspect further comprise depositing a metal film on an exposed region ofthe p-type GaN layer, the n-type GaN layer or both and optionallyannealing the metal film to form an electrical contact on the p-type GaNlayer, the n-type GaN layer or both. One method of this aspect comprisesthe optional step of etching a portion of the GaN multilayer to expose aregion of the n-type GaN layer, a region of the p-type GaN layer orboth, depositing a metal film on an exposed region of the n-type GaNlayer, the p-type GaN layer or both and optionally annealing the metalfilm to form an electrical contact on the n-type GaN layer, the p-typeGaN layer or both.

Embodiments of specific methods of this aspect further comprise thesteps of providing one or more metallic contacts in electrical contactwith a portion of the one or more LED device structures; coating the oneor more LED device structures and one or more metallic contacts with aphotosensitive polymer layer; and exposing select portions of thephotosensitive polymer layer to electromagnetic radiation, wherein theelectromagnetic radiation is at least partially transmitted through thedevice substrate and wherein the one or more metallic contacts block atleast a portion of the electromagnetic radiation from reaching at leasta portion of the photosensitive polymer layer, the one or more metalliccontacts thereby serving as one or more self-aligned mask elements. Anoptional step comprises removing portions of the photosensitive polymerlayer which are masked by the one or more metallic contacts serving asself-aligned mask elements. Optionally, the step of removing portions ofthe photosensitive polymer layer which are masked by the one or moremetallic contacts serving as self-aligned mask elements comprisesdeveloping the photosensitive polymer layer, wherein regions of thephotosensitive polymer layer that were not exposed to electromagneticradiation are dissolved by exposure to a solvent.

In some embodiments, the LED device structures correspond to a verticaltype LED. In embodiments, the GaN multilayer comprises a plurality ofGaN layers, for example GaN layers including, but not limited to, GaNcontact layers, GaN spreader layers, GaN cladding layers, GaN barrierlayers, GaN etch block layers, GaN buffer layers and any combination ofthese.

In embodiments, the mask provided on the GaN multilayer comprises afirst layer of Si₃N₄ and an optional metal second layer. Optionally,methods of this aspect comprise removing at least a portion of the mask.In embodiments, the step of removing material comprises etching exposedregions of a masked GaN multilayer via and etching method such asinductively coupled plasma reactive ion etching, reactive ion etching ordeep reactive ion etching. After the removing step and/or the releasingstep, some LED device structures optionally are anchored to the handleor growth substrate by at least one homogeneous anchor or at least oneheterogeneous anchor. Some embodiments optionally comprise a step ofanchoring one or more of the LED device structures by at least onehomogeneous anchor or at least one heterogeneous anchor. In someembodiments, the step of at least partially releasing comprisesphotoelectrochemically or electrochemically etching at least a portionof the GaN multilayer.

In embodiments, the device substrate is a glass substrate, a polymersubstrate, a flexible substrate, a large area substrate, a pre-metalizedsubstrate, a substrate pre-patterned with one or more device componentsor any combination of these. Transfer of the LED device structures tothe device substrate is optionally via contact printing using aconformal transfer device, for example a PDMS stamp. In certain methodsof this aspect, the device substrate comprises one or more additionalLED device structures and the step of transferring at least a portion ofthe one or more LED device structure comprises printing at least one ofthe one or more LED device structures on to of the one or moreadditional LED device structures, for example to make a stacked LEDdevice structure. Another method of this aspect, comprises a step ofprinting one or more additional LED device structures on top of the oneor more LED device structures on the device substrate, for example tomake a stacked LED array.

In some embodiments, a stacked LED comprises multiple LEDs stacked oneon top of another, each capable of outputting selected wavelengths ofelectromagnetic radiation, for example each capable of outputtingdifferent wavelengths of electromagnetic radiation. In a specificembodiment, a stacked LED comprises multiple LEDs whose totalelectromagnetic spectrum is visible as white light.

Optionally, multiple LEDs are connected in series, such that identicalcurrent flows through each LED. Optionally, multiple LEDs are connectedin parallel, such that each LED experiences identical voltage. MultipleLEDs connected in series provide a benefit of similar output ofelectromagnetic radiation from each LED.

In some embodiments, an array of LEDs comprises a phosphor or an arrayof phosphors. A particular method embodiment comprises a step ofprinting phosphors over at least a portion of an LED array, for examplevia a contact printing method. Another method embodiment comprisesmaking an array of phosphors, making an array of LEDs and laminating thearray of phosphors over the array of LEDs.

In another aspect, provided are methods for making an array ofphosphors. One method of this aspect comprises the steps of molding anelastomer layer with an array of recessed regions; providing phosphorparticles over the elastomer layer, wherein the phosphor particles atleast partially fill in the array of recessed regions; and providing anencapsulation layer over the elastomer layer, wherein the phosphorparticles are encapsulated in the array of recessed regions, therebymaking an array of phosphors. In exemplary embodiments, the recessedregions have depths selected over the range of 5 nm to 10 μm.

In another aspect, provided are methods for making a semiconductordevice. A method of this aspect comprises the steps of providing atransparent substrate; assembling a semiconductor device on a surface ofthe transparent substrate via dry transfer contact printing; providingone or more metallic contacts in electrical contact with thesemiconductor device; coating said semiconductor device and one or moremetallic contacts with a photosensitive polymer layer; exposing selectportions of the photosensitive polymer layer to electromagneticradiation, wherein the electromagnetic radiation is at least partiallytransmitted through the transparent substrate and wherein the one ormore metallic contacts block at least a portion of the electromagneticradiation from reaching at least a portion of the photosensitive polymerlayer, the one or more metallic contacts thereby serving as one or moreself-aligned mask elements. Certain embodiments further comprises a stepof removing portions of the photosensitive polymer layer which aremasked by the one or more metallic contacts serving as self-aligned maskelements. In one embodiment, the step of removing portions of thephotosensitive polymer layer which are masked comprises developing thephotosensitive polymer layer and wherein regions of the photosensitivepolymer layer that were not exposed to the electromagnetic radiation aredissolved by exposure to a solvent.

Useful transparent substrates for methods of this aspect includesubstrates comprising quartz, glass, sapphire and any combination ofthese. In certain embodiments, the transparent substrate, thesemiconductor device or both transmit at least 50% of theelectromagnetic radiation. In some embodiments, at least a portion ofthe electromagnetic radiation is reflected, absorbed or both by the oneor more metallic contacts. In a specific embodiment, at least 50%, atleast 75%, or at least 95% of the electromagnetic radiation received bya metallic contacts is reflected, scattered and/or absorbed by themetallic contact. Useful metallic contacts include those comprisinggold, copper, nickel, aluminum, platinum and any combination of these.In specific embodiments, each of the metallic contacts has a thicknessselected over the range of 5 nm to 10 μm.

In specific embodiments, the photosensitive polymer has a thicknessselected over the range of 5 nm to 1 mm. Useful photosensitive polymersinclude, but are not limited to, negative tone photopolymers, polymersat least partially crosslinked by exposure to electromagnetic radiation,BCB (Benzo Cyclo Butene), WL-5351, SU-8, polyurethanes, silicones andany combination of these.

In another aspect, provided herein are methods for assembling anelectronic device. A method of this aspect comprises the steps of:providing one or more electronic device components; contacting the oneor more electronic device components with a conformal transfer andmolding device, thereby transferring the one or more electronic devicecomponents onto the conformal transfer device; contacting a prepolymerlayer disposed over a host substrate with the conformal transfer andmolding device having the one or more electronic device componentspositioned thereon, thereby at least partially embedding the one or moreelectronic device components into the prepolymer layer and patterningthe prepolymer layer with one or more recessed features; curing theprepolymer layer, thereby forming a polymer layer having one or morerecessed features; and filling at least a portion of the one or morerecessed features with a filling material.

Optionally, methods of this aspect further comprise the steps ofproviding a filling material on a surface of the polymer and dragging ormoving a scraping tool along the surface of the polymer to fill thefilling material into at least a portion of the one or more recessedfeatures.

Useful filling materials include, but are not limited to, conductivematerials, optical materials, heat transfer materials and anycombination of these. Useful host substrates include substratescomprising polymer, glass, plastic, semiconductor, sapphire, ceramicsand any combination of these. Useful prepolymer layers include, but arenot limited to, those layers comprising a photocurable polymer, athermally curable polymer, a photocurable polyurethane and anycombination of these.

Optionally, methods of this aspect comprise a step of curing theprepolymer layer by exposing the prepolymer layer to electromagneticradiation, heating the prepolymer layer or both. In one embodiment, amethod of this aspect further comprises a step of curing the fillingmaterial, for example by heating the filling material, exposing thefilling material to electromagnetic radiation or both.

In embodiments, at least one of the one or more electronic devicecomponents comprises one or more electrode contacts. Optionally, atleast a portion of the polymer is etched in a further step to expose atleast one of the one or more electrode contacts. In a specificembodiment, the filling material comprises a conductive material, forexample in electrical communication with one or more electrode contacts.Conductive filling materials are useful, for example for providing oneor more electrical interconnections to at least one of the electronicdevice components. Useful conductive materials include those materialshaving a resistivity selected over the range of 1×10⁻¹⁰ to 1×10⁻² Ω·cmor 1×10⁻¹⁰ to 1×10⁻⁵ Ω·cm, for example a conductive past such as epoxiescontaining metallic particles, such as silver epoxy, gold epoxy, copperepoxy or aluminum epoxy; conductive carbon materials, such as carbonblack, carbon nanotubes, graphite or grapheme; and any combination ofthese.

In a specific embodiment, the filling material comprises an opticalmaterial. Optionally, the optical material forms an optical element suchas a collecting optic, a concentrating optic, a reflective optic, adiffusing optic, a dispersive optic, a lens, a phosphor, a waveguide, anoptical fiber, an optical coating, a transparent optic, an opticalfilter, a polarizing optic and any combination of these. Useful opticalmaterials include polymer, plastic, glass and any combination of these.

Useful electronic device components include, but are not limited to, aP-N junction, a thin film transistor, a single junction solar cell, amulti-junction solar cell, a photodiode, a light emitting diode, alaser, a sensor, a photodiode, an electro-optical device, a CMOS device,a MOSFET device, a MESFET device, a photovoltaic cell, amicroelectromechanical device, a HEMT device, a light-emittingtransistor and any combination of these. In a specific embodiment, theelectronic device component has a dimension selected over the range of10 nm to 10 mm or 10 nm to 10 μm, for example a height, width, diameter,and/or depth. In specific embodiments, the electronic device componenthas a height selected over the range of 10 nm to 10 μm, a width selectedover the range of 1 μm to 10 mm, a depth selected over the range of 1 μmto 10 mm and/or a diameter selected over the range of 1 μm to 10 mm.

Another method of this aspect comprises the steps of: providing aconformal transfer and molding device having a contact surfacecomprising one or more transfer surfaces and one or more raised moldingfeatures; contacting one or more electronic device components with theconformal transfer and molding device, thereby positioning the one ormore electronic device components on the one or more transfer surfacesof the conformal transfer and molding device; contacting a prepolymerlayer disposed over a host substrate with the patterned conformaltransfer and molding device having the one or more electronic devicecomponents positioned thereon, thereby at least partially embedding theone or more electronic device components and the one or more raisedmolding features into the prepolymer layer; curing the prepolymer layer,thereby forming a polymer layer, wherein the one or more raised moldingfeatures of the conformal transfer device are replicated as one or morerecessed features in the polymer layer; separating the conformaltransfer device from the polymer layer, wherein the one or moreelectronic device components are retained in the polymer layer; applyinga filling material to a surface of the polymer layer; and dragging ascraping tool along the surface of the polymer to fill the fillingmaterial into at least a portion of the one or more recessed features.

Another method of this aspect comprises the steps of: providing a hostsubstrate with a prepolymer disposed thereon; at least partiallyembedding one or more electronic device components into the prepolymerlayer, wherein one or more recessed features are patterned in theprepolymer layer during the embedding step; curing the prepolymer layer,thereby forming a polymer layer having one or more recessed features andfixing the one or more electronic device components in the polymerlayer; and filling at least a portion of the one or more recessedfeatures with a conductive material, wherein the conductive materialprovides one or more electrical interconnections to at least oneelectronic device component.

In another aspect, provided are methods for making a printableelectronic device on a device substrate. A method of this aspectcomprises the steps of: providing a printable electronic device having acontact area, wherein the printable electronic device is anchored to ahost substrate via one or more homogeneous or heterogeneous anchors;contacting the contact area of the printable electronic device with acontact surface of a conformable transfer device, wherein the contactsurface of the conformable transfer device has an area smaller than thecontact area of the printable electronic device, and wherein the contactarea and the contact surface are aligned off center from each other,wherein contact between the contact surface and the contact area bindsthe printable electronic device to the contact surface; separating theprintable electronic device and the host substrate, thereby releasingthe one or more homogeneous or heterogeneous anchors; contacting theprintable electronic device disposed on the contact surface with areceiving surface of the device substrate; and separating the contactsurface of the conformable transfer device and the printable electronicdevice, wherein the printable electronic device is transferred onto thereceiving surface, thereby assembling the printable electronic device onthe receiving surface of the device substrate.

In embodiments, the contact surface of the conformable transfer deviceis a percentage of the contact area of the printable electronic device,for example 25%, 30%, 40%, 50%, less than 50% or selected over the rangeof 25 to 75%. In a specific embodiment, the contact surface of theconformable transfer device and the contact area of the electronicdevice are aligned off center from each other, for example by 1 μm, 2μm, 10 μm, greater than 1 μm, greater than 10 μm or selected over therange of 1 μm to 100 μm. Optionally the contact surface of theconformable transfer device is provided on a relief feature of theconformable transfer device. In one embodiment, the conformable transferdevice is a PDMS stamp.

In some embodiments, the conformable transfer device comprises aplurality of relief features providing a plurality of contact areas.Optionally, in an embodiment where the conformable transfer devicecomprises a plurality of relief features providing a plurality ofcontact regions, the method comprises providing a plurality of printableelectronic devices each having a contact area, wherein each of theprintable electronic devices is anchored to a host substrate via one ormore homogeneous or heterogeneous anchors; contacting the contact areasof the printable electronic devices with the contact areas of theconformable transfer device, wherein each of the contact regions of theconformable transfer device has an area smaller than the each of contactareas of the printable electronic device, and wherein the contact areasand the contact regions are aligned off center from each other, whereincontact between the contact regions and the contact areas binds theprintable electronic devices to the contact regions; separating theprintable electronic devices and the host substrate, thereby releasingthe homogeneous or heterogeneous anchors; contacting the printableelectronic devices disposed on the contact regions with a receivingsurface of the device substrate; and separating the contact regions ofthe conformable transfer device and the printable electronic devices,wherein the printable electronic devices are transferred onto thereceiving surface, thereby assembling the printable electronic deviceson the receiving surface of the device substrate.

Useful printable electronic devices include, but are not limited to aP-N junction, a thin film transistor, a single junction solar cell, amulti-junction solar cell, a photodiode, a light emitting diode, alaser, a CMOS device, a MOSFET device, a MESFET device, a photovoltaiccell, a microelectromechanical device, a HEMT device or any combinationof these. In embodiments, the device substrate is a flexible substrate,a large area substrate, a pre-metalized substrate, a substratepre-patterned with one or more device components, or any combination ofthese.

STATEMENT REGARDING COLOR DRAWINGS

The patent or application file contains at least one drawing executed incolor. Copies of this patent or patent application publication withcolor drawing(s) will be provided by the Office upon request and paymentof the necessary fee.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1. (A) SEM image of a square array of AlInGaP LED structures (50 μmby 50 μm) created by vertical, patterned etching through an epitaxialmultilayer stack grown on a GaAs wafer. (B) Cross-sectional SEM view ofone of these structures, showing the LED semiconductor layers (quantumwells, as well as cladding, spreading, and contact layers) on asacrificial epilayer of AlAs. (C) Schematic illustration of aprinting-based assembly method for transferring collections of LEDs(gray) released from the GaAs wafer to a target substrate (shown here asa flexible sheet). (D) SEM image of the GaAs wafer after removing a setof LEDs (indicated by white arrows) with a stamp. (E) SEM image of aregion of the target substrate printed with this stamp. (F) Angled-viewSEM image of an individual LED (i.e., ILED) from the array in (D). Apair of “breakaway” photoresist (PR) anchors at the two far corners ofthe device holds it above the GaAs wafer in the suspended configurationof a diving board, for ease of liftoff with a stamp. The white arrowpoints to the region of removed AlAs. (G) SEM image of a densecollection of such devices on a piece of a GaAs wafer. The black arrowand white dot indicate, roughly, the region of this chip thatcorresponds to the image of (F). (H) Optical image of a target substrateprinted with sparse arrays of devices at different spacings, derivedfrom the chip shown in (G). (I) Large-scale collection of ILEDs (1600devices, in a square array with pitch of 1.4 mm) printed onto a thin,flexible sheet of plastic, shown here wrapped onto a cylindrical glasssubstrate (main panel). The inset shows a similar collection of ILEDs(1600 devices, in a square array with pitch of 1.4 mm) printed onto aplate of glass. For these cases, relatively large ILEDs were selectedfor ease of viewing; devices with dimensions of (E) are invisible atthis magnification.

FIG. 2. (A) Exploded view schematic illustration of an array of ILEDscontacted by a metal mesh (bottom; n contacts) and a metal film (top; pcontacts). A thin adhesive layer of PDMS facilitates printing onto theglass substrate. A photopatterned layer of epoxy on top of the devicesprevents shorting of the top film to the bottom mesh. (B)Opticalmicrographs of an array of ILEDs (top: 25 μm by 25 μm, squaregeometries; bottom: characters “LED”) in their off state with frontsideillumination (left) and in their on state without illumination (right).(C) Schematic illustration of an ILED with integrated ohmic contacts(left) and optical image of an operating device (right), showing uniformemission characteristics at all regions not directly blocked by thecontacts or probe tips. The areas delineated by yellow and white dashedboxes correspond to the contact electrodes and the device periphery,respectively. The regions labeled “PT” correspond to the probe tips usedto evaluate the device operation. (D) Current-voltage-emissioncharacteristics of a representative device before undercut etching onthe GaAs wafer, and after transfer printing onto a polyurethane-coatedglass slide. The inset provides a histogram of the bias voltages neededto produce currents of 0.1 mA in a collection of devices. (E) Spectralcharacteristics of emission for a typical device on the wafer and aftertransfer printing.

FIG. 3. (A) Schematic illustration of a planar scheme forinterconnecting a printed array of ILEDs in a passive matrix layout.Coordinated control of voltages applied to the row and column electrodesallows operation in a passive matrix display mode. (B) Images of aflexible display that incorporates a 16 by 16 array of ILEDs in thelayout shown in (A), on a sheet of plastic (PET), wrapped around thethumb of a mannequin hand (main panel; human scale; radius ˜8 mm) and acylindrical glass tube (inset; radius ˜12 mm). External interface tocontrol electronics occurs through ribbon cables bonded to column androw electrodes that emerge from the periphery of the display. (C) Imageof a comparatively large, semitransparent display that uses a similarlayout but with a sparse array of ILEDs on a glass substrate. The camerais focused on the paper in the background; the white dashed boxillustrates the perimeter of the active region of the display. (D) Imageof a similar device (bottom right) displaying a different pattern infront of a mirror (upper left), to illustrate the bidirectional emissionproperty. In this system, the ILEDs represent only ˜0.8% of the totalarea. The inset shows a magnified view of a region of the display in itsoff state, to illustrate the small areal coverage of the devices. Theblack arrow points to one of the ILEDs, which is barely visible at thismagnification.

FIG. 4. (A) Color plots of the strain distributions (in percent) at thequantum well region and the corresponding finite element mesh used forsimulation (top) and optical micrographs (bottom) of a stretchable ILEDon a rubber substrate in unstrained and strained states. The bottompanels show optical micrographs in the off (top) and on (bottom) states,with and without external illumination, respectively. (B) Passivematrix, stretchable ILED display that uses a noncoplanar meshconfiguration, on a rubber substrate. Here, interconnect lines betweenadjacent devices are supported by arc-shaped bridge structures that candeform in response to applied strain. Both the main panel and the insetimages were collected with an automated camera system that combinespictures captured at different focal depths to provide a sharp,composite image. (C) Optical micrographs of a set of four pixels in thedisplay shown in (B). The upper and lower images show opticalmicrographs in the off (top) and on (bottom) states, with and withoutexternal illumination, respectively. The multiple red spots in the caseof the configuration in the left result from reflections from theinterconnection bridges. (D) Current (I)-voltage (V) measurements on arepresentative ILED in the display, at different applied strains. (E)Voltage (V) needed to generate a current of 20 μA measured afterstretching cycles to 500 times at an applied strain of 22%. The insetshows the I-V behavior after these cycling tests. These devices haverelatively high turn-on voltages, due to the use of nonohmic contacts.

FIG. 5. Schematic illustration (left) and cross sectional scanningelectron microscope (SEM) image (middle) of the epitaxial semiconductormultilayer stack on a GaAs wafer. (Right) SEM image of a square array oflaterally delineated, square ILEDs on a GaAs wafer. (Bottom) Details ofthe epi-stack.

FIG. 6. Schematic illustration and optical microscope/SEM images ofprocessing steps for retrieving ILEDs from a GaAs source wafer.

FIG. 7. Picture of the automated printing machine, with key partslabeled.

FIG. 8. (A) Schematic illustration of retrieving and printing selectedsets of ILEDs with a composite stamp. (B) Optical microscope image ofthe source wafer after three cycles of printing. (C) Optical microscopeimage of a substrate with sparsely printed ILEDs derived from the sourcewafer of (B), illustrating the concept of area expansion.

FIG. 9. Schematic illustration of processing steps for ILEDs of FIG. 2A.

FIG. 10. (A) Optical microscope image of transmission line model (TLM)patterns with gaps of L₁=10 μm, L₂=20 μm, L₃=30 μm, L₄=40 μm, L₅=50 μm,L₆=60 μm, L₇=70 μm. (B) I (current)-V (voltage) curves associated with pcontacts (Pt/Ti/Pt/Au=10/40/10/70 nm) as a function of annealingtemperature. (C) Resistance as a function of gap length, for the pcontact metallization, evaluated at different annealing temperatures.(D) I-V curves associated with n contacts (Pd/Ge/Au=5/35/70 nm) as afunction of annealing temperature. (E) Resistance as a function of gaplength, for the n contact metallization, evaluated at differentannealing temperatures.

FIG. 11. (A) I-V curves of ILED devices with ohmic contacts with andwithout a passivation scheme to protect the sidewalls during undercutetching. (B) I-V curves of ILED devices (50×50 μm and 100×100 μm) withohmic contacts and passivation scheme, before and after transfer.

FIG. 12. (A) Schematic illustration of processing steps for fabricatingelectrical interconnections to complete a passive matrix array. (B)Optical microscope image of an array of ILEDs array after exposingn-GaAs by wet etching. (C) Cross sectional SEM view of an ILED afterexposing n-GaAs by wet etching. (D) Optical microscope image of an arrayof ILEDs with electrical interconnections.

FIG. 13. Optical images of a 16×16 ILED (100 μm×100 μm with a pitch of210 μm) display on a plastic substrate, wrapped onto the wrist (A) andfinger (B, C) of mannequin. (Bottom right) a map of non-working pixels(indicated by ‘x’ symbols).

FIG. 14. (A) Optical image of a 16×16 ILED (50 μm×50 μm with a pitch of70 μm) display on a glass substrate with ACF ribbon cable connection.(B) Optical images of the display during the operation. (Left-top) a mapof non-working pixels (indicated by ‘x’ symbols).

FIG. 15. Electrical properties of a 16×16 ILED (100 μm×100 μm with apitch of 210 μm) display on a plastic substrate. (A) Plot of voltage at20 μA and (B) I-V curves under R=∞, 17.3, 12.6, 8.8, 7.3 mm. (C) Plot ofvoltage at 20 μA and (D) I-V curves as a function of bending cycles upto 500 times at R=8.8 mm. The relatively high turn-on voltages are dueto the use of non-ohmic contacts.

FIG. 16. (A, B) Optical images of a 16×16 ILED (100 μm×100 μm with apitch of 1.20 mm) display on glass substrate during operation. (C) A mapof non-working pixels (indicated by ‘x’ symbols).

FIG. 17. (A) Exploded schematic illustration of processing steps forwavy ILEDs ribbons. (B) Optical microscope image of wavy ILEDs ribbonswith 50 μm and 100 μm width collected with a scanning focal technique.Optical microscope image of a wavy ILEDs ribbon in different strainedstates (from wavy to flat): (C) non-emission with illumination, (D)emission with illumination, (E) emission without illumination. (F) I-Vcurves under different strained states. The relatively high turn-onvoltages are due to the use of non-ohmic contacts.

FIG. 18. (A) Optical microscope images of emission, collected withoutillumination, from wavy ILEDs ribbons in wavy (top) and flat (bottom)configurations. Color analysis of pixels recorded in white square box of(A) using a utilities available in a commercial software package(Photoshop, Adobe Systems): range of red values of emission from (B) thewavy and (C) flat configurations, as a function of position along theribbon length (0=white, 255=full red). (D) Averaged range of red valuesof emission across the ribbon width from (B) and (C).

FIG. 19. (A) Schematic illustration of processing steps for stretchableILEDs display. (B) A map of non-working pixels (indicated by ‘x’symbols).

FIG. 20. Optical microscope images of a passive matrix, stretchableILEDs display that uses a non-coplanar mesh configuration, on a flatrubber substrate.

FIG. 21. Optical microscope and SEM images of a passive matrix,stretchable ILEDs display that uses a non-coplanar mesh configuration,on a bent/twisted rubber substrate.

FIG. 22. (A) Schematic illustrations of a stretchable ILED on a rubbersubstrate in compressed (left) and stretched (right) configurations.Strain distributions in the device: (B) top surface, (C) middle surface(quantum well region), (D) bottom surface in a compressed state and (E)middle surface in a stretched state.

FIG. 23. Strain distributions of a stretchable ILED display: (A) topsurface, (B) middle surface (quantum well region), and (C) bottomsurface of ILED.

FIG. 24. Schematic illustration of procedures for printing andinterconnecting microscale device components. (a) The first stepinvolves fabrication of devices (square, dark grey blocks withrectangular, gold electrodes) on a source substrate. (b) An elastomericstamp (light blue) retrieves a collection of these devices by van derWaals adhesion to features of relief that contact the electrode regions.(c) Bringing the stamp, ‘inked’ with devices in this manner, intocontact with a layer of liquid prepolymer (tan), followed by curing to asolid form yields a molded structure with integrated, embedded devices.(d) Scraping a conductive paste (light grey) over this structure fillsthe molded features to form electrical contacts to the devices andinterconnects between them.

FIG. 25. (a) Optical image of a collection of conducting features formedby molding a layer of PU on a PET substrate, and then filling theresulting trenches with silver epoxy. These results illustrate the rangeof feature sizes and shapes and areas that can be formed easily. (b)Cross-sectional SEM images of filled lines with depths of 20 μm andwidths of 20 μm (left) and 200 μm (right). Higher aspect ratios andnarrower features can be achieved with suitable modifications to theconductive material. (c) Interconnected arrays of metal pads (Cr/Au,100/1000 nm; 500×500 μm; 1.5 mm pitch) with crossed, but electricallyisolated conducting lines on a PET substrate. This result used astamp/mold with lines (100 μm widths and 20 μm depths) and rectangularfeatures (100×300 μm lateral dimensions and 40 μm depths) to form theinterconnects and the contacts to the metal pads, respectively. Thebottom left and right frames provide a schematic cartoon illustrationand a top view optical micrograph, respectively, of the structure near arepresentative pad. (d) Current/voltage data collected by probingcontact pads to different combinations of row (r1, r2, etc) and column(c1, c2, etc) interconnect lines verifies electrical continuity alongcolumns and rows and electrical isolation between columns and rows.

FIG. 26. (a) Optical image of a set of six AlInGaP light emitting diodes(LEDs; 250×250 μm) formed in ultrathin (2.5 μm thick) layouts and pairsof molded interconnect lines leading to each. Selective printing formedthe arrays; aligned molding followed by filling with silver epoxy formedthe interconnect. The top inset provides a top view optical micrograph.The three devices in the middle were connected to a power supply tocause light emission. (b) Current/voltage characteristics (non-ohmiccontacts) of these LEDs.

FIG. 27. (a) Schematic illustration of a photovoltaic minimoduleconsisting of five monocrystalline bars of silicon with integratedcontacts. The left and right frames show the structure before and afterfilling molded trenches with silver epoxy, respectively. The moldedpolymer (PU) is illustrated in tan; the silicon cells are black, withgold contacts. Filling the molded trenches with silver epoxy (lightgrey) yields the interconnected structure on the right. Each bar is 50μm wide, 1.55 mm long and 20 μm thick, with ohmic contacts of metal(Cr/Au, 100/1000 nm; 50 μm width and 100 μm length for p contact; 50 μmwidth and 1.4 mm length for n contact) on p and n doped regions. (b)Optical image of a sample, with an inset that shows a cross sectionalview of part of the structure. (c) Current/voltage characteristicscarried out at room temperature, in light and dark. The efficiency(E_(ff)) and fill factor (FF) of this solar cell were 6.5% and 0.61respectively.

FIG. 28. Epitaxial layers of GaAs LED wafer.

FIG. 29. Processing schematics for μ-GaAs LED.

FIG. 30. A. Scanning Electron Microscopy (SEM) image of isolated GaAsLED on the host wafer. B. Scanning Electron Microscopy (SEM) image GaAsLED after heterogeneous anchors are photolithographically defined. C.Scanning Electron Microscopy (SEM) image of transfer-printed GaAs LEDson a PET substrate. D. Optical Microscopy (OM) image of GaAs LEDs before& after transfer-printing process.

FIG. 31. (A). A cartoon illustrating the printed μ-GaAs LED. (B)Luminance vs. current-voltage characteristic plots.

FIG. 32. Epitaxial layer structure of a typical GaN device on a siliconwafer.

FIG. 33. Processing scheme of individually printable μ-GaN LEDs.

FIG. 34. Scanning electron microscopy (SEM) image of an anchor of μ-GaNLED cell before (left) and after (right) KOH undercut process.

FIG. 35. Optical image of the donor substrate after severalstep-and-repeat transfer-printing process has been carried out.

FIG. 36. Step-and-repeat process on GaAs μ-LEDs.

FIG. 37. (a) Optical image (b) current-voltage characteristic and (c)emission spectrum of an individual μ-GaN LED cell under operation.

FIG. 38. SEM images of GaN LED devices before and after KOH undercut.Extended exposure to KOH causes moderate roughening of the GaNsidewalls.

FIG. 39. Sidewall passivation scheme for printable GaN devices.

FIG. 40. Printable GaN devices utilizing laser lift-off.

FIG. 41. Freestanding GaN device transfer utilizing PEC etching withInGaN sacrificial layer. SEM images* of PEC etching for freestanding GaNand AlGaN layers are inserted. (*left image: E. Haberer et al. Appl.Phys. Lett. 85, 5179 (2005), right image: R. Sharma et al Appl. Phys.Lett. 87, 051107 (2005)).

FIG. 42. Selective etching of sacrificial layer by EC (electrochemical)etching.

FIG. 43. Selective etching of sacrificial layer (i.e. ZnO) with specificetchant (NH₄Cl).

FIG. 44. Optical Microscopy (OM) image of heterogeneous anchoringstructures.

FIG. 45. Various geometries of heterogeneous anchoring structures.

FIG. 46. (A) Optical microscopy (OM) image of homogeneous anchors; (B)scanning electron microscopy (SEM) images of homogeneous anchors.

FIG. 47. SEM images of commercially available wire-bonded LED.

FIG. 48. (a) Schematic illustration of the cell design. (b) Process forencapsulation via back-side exposure.

FIG. 49. (a) Scanning electron microscopy (SEM) image (b) opticalmicroscopy (OM) image of passivated μ-GaN LED using encapsulation viaback-side exposure process.

FIG. 50. Scanned profile using a profilometer of μ-GaN LED after theencapsulation via back-side exposure process.

FIG. 51. Five μ-GaN LEDs connected in series.

FIG. 52. Two strings of five μ-GaN LEDs connected in series.

FIG. 53. Fabrication schematic for the molded interconnection.

FIG. 54. Fabrication schematic for the molded interconnection.

FIG. 55. (a) Optical Image of 1 GaAs LED cell. 9 GaAs LED cells with250×250 μm² are independently metalized with a conductive silver paste.(b) Current-Voltage (I-V) characteristic of 1 GaAs LED.

FIG. 56. Molded interconnection approach with addition of reflectivelayers for selective curing.

FIG. 57. Resolution of molded interconnection approach.

FIG. 58. GaAs vertical LED structure.

FIG. 59. Fabrication process for the mesh interconnection approach. Alsoexploded view schematic illustration of an array of ILEDs contacted by ametal mesh (bottom; n contacts) and a metal film (top; p contacts) isshown.

FIG. 60. A comparison between strings of μ-LEDs connected in series andin parallel.

FIG. 61. Optical Image of serially connected strings of μ-LEDs printedon a plastic substrate.

FIG. 62. Planar interconnection processing schematics for passive-matrixdisplay using printed μ-LEDs.

FIG. 63. Spatially independent micro-lens array fitted to a of fiveμ-GaN LEDs display with stretchable mechanical interconnects.

FIG. 64. Stretchable μ-LEDs.

FIG. 65. a) Mirror-like facets increase internal reflection, but b)roughened surfaces reduces internal reflection.

FIG. 66. Formation of pyramidal structures is performed by PEC KOHetching of a fully fabricated/undercut device in the presence of UVlight.

FIG. 67. Light Enhancement μ-GaN LED with outcoupling: GaN conestructures.

FIG. 68. GaN LED encapsulation in a polymer micro-lens increases lightextraction efficiency.

FIG. 69. Processing steps to form a micro-lens array fitted to amicro-LED display.

FIG. 70. Processing steps to form a spatially independent micro-lensarray fitted to a micro-LED display.

FIG. 71. Schematics for optically enhancement with polymeric pattern.

FIG. 72. Bi-directional nature of light output from the printed μ-LED ontransparent substrates.

FIG. 73. Integration of reflector and thermal heat sink onto printedμ-LEDs.

FIG. 74. Multiple stacks of μ-LEDs

FIG. 75. Thermographic images at various driving conditions of AlInGaPμ-LED.

FIG. 76. Thermal management of printed μ-LED on plastic substrates.

FIG. 77. Printed μ-diamond as a heat sink.

FIG. 78. Integration of reflector & thermal heat sink onto printedμ-LEDs.

FIG. 79. Heterogeneous integration of μ-LEDs with printed electronics.

FIG. 80. Heterogeneous integration of photodiode with μ-LEDs for the insitu self-calibration of the light output.

FIG. 81. Fabrication scheme of uniform phosphor array.

FIG. 82. Phosphors in elastomer cavities.

FIG. 83. Laminated Phosphor-encapsulated Elastomer on top of printed andpackaged LEDs.

FIG. 84. Exemplary method of making semiconductor devices.

FIG. 85. Exemplary method of making GaN LED devices.

FIG. 86. Exemplary method of making GaN LED devices.

FIG. 87. Exemplary method of making GaN LED devices.

FIG. 88. Exemplary method of making GaN LED devices.

FIG. 89. Illustration of a scheme for processing electronic devices on ahandle substrate.

FIG. 90. FIG. 90A) Cross sectional view of an exemplary semiconductorstructure grown on a growth substrate; FIG. 90B) Illustration of atransfer scheme for transferring portions of a semiconductor structureto two separate handle substrates.

FIG. 91. Illustration of a scheme for assembly of electronic devicesgrown on separate growth substrates on a common handle substrate.

FIG. 92. FIG. 92A) Illustration of a scheme for assembly of electronicdevices grown on separate growth substrates on a common handlesubstrate; FIG. 92B) Cross sectional view of the assembled electronicdevices on the handle substrate.

FIG. 93. Illustration of a scheme for processing electronic devices on ahandle substrate.

FIG. 94. Illustration of a scheme for processing electronic devices on ahandle substrate.

DETAILED DESCRIPTION OF THE INVENTION

In general the terms and phrases used herein have their art-recognizedmeaning, which can be found by reference to standard texts, journalreferences and contexts known to those skilled in the art. The followingdefinitions are provided to clarify their specific use in the context ofthe invention.

“Transferable” or “printable” are used interchangeably and relates tomaterials, structures, device components and/or integrated functionaldevices that are capable of transfer, assembly, patterning, organizingand/or integrating onto or into substrates. In an embodiment,transferring or printing refers to the direct transfer of a structure orelement from one substrate to another substrate, such as from amultilayer structure to a device substrate or a device or componentsupported by a device substrate. Alternatively, transferable refers to astructure or element that is printed via an intermediate substrate, suchas a stamp that lifts-off the structure or element and then subsequentlytransfers the structure or element to a device substrate or a componentthat is on a device substrate. In an embodiment, the printing occurswithout exposure of the substrate to high temperatures (i.e. attemperatures less than or equal to about 400 degrees Celsius). In oneembodiment, printable or transferable materials, elements, devicecomponents and devices are capable of transfer, assembly, patterning,organizing and/or integrating onto or into substrates via solutionprinting or dry transfer contact printing. Similarly, “printing” is usedbroadly to refer to the transfer, assembly, patterning, organizingand/or integrating onto or into substrates, such as a substrate thatfunctions as a stamp or a substrate that is itself a target (e.g.,device) substrate. Such a direct transfer printing provides low-cost andrelatively simple repeated transfer of a functional top-layer of amultilayer structure to a device substrate. This achieves blankettransfer from, for example, a wafer to a target substrate without theneed for a separate stamp substrate.

“Substrate” refers to a material having a surface that is capable ofsupporting a component, including a device, component or aninterconnect. An interconnect that is “bonded” to the substrate refersto a portion of the interconnect in physical contact with the substrateand unable to substantially move relative to the substrate surface towhich it is bonded. Unbonded portions, in contrast, are capable ofsubstantial movement relative to the substrate. The unbonded portion ofan interconnect generally corresponds to that portion having a “bentconfiguration,” such as by strain-induced interconnect bending.

“Host substrate” and “handle substrate” interchangeably refer to asubstrate on which an electronic device is assembled, processed orotherwise manipulated. In certain embodiments, a handle substrate is asubstrate useful as a transitory substrate, for example for holdingstructures for subsequent transfer to another substrate, such as bytransfer printing. In some embodiments, a handle substrate is useful asa processing substrate, where structures present on the handle substrateundergo additional processing steps. “Growth substrate” refers to asubstrate useful for growing material, for example via epitaxial growth.In embodiments, a growth substrate comprises the same material as isbeing grown. In embodiments a growth substrate comprises materialdifferent from that being grown. Useful growth substrates includesubstrates which are lattice matched, or effectively lattice matched, tothe material being grown. In some embodiments a growth substrate is ahost substrate. “Device substrate” refers to a substrate useful forassembling device components. In some embodiments, a device substratecomprises functional device components. In some embodiments, a devicesubstrate is a flexible substrate, a large area substrate, apre-metalized substrate, a substrate pre-patterned with one or moredevice components, or any combination of these. In some embodiments adevice substrate is a host substrate.

The term “surface” as used herein is intended to be consistent with itsplain meaning which refers to an outer boundary of an object. Inembodiments, surfaces may be given specific names, such as “receivingsurface”, “contact surface”, “external surface”. In some embodiments,named surfaces can refer to their target use and/or identify subregionsof a surface. In some embodiments, named surfaces can refer to theirorientation, for example relative to other nearby or adjacentcomponents.

“Functional layer” or “device layer” refers to a layer capable ofincorporation into a device or device component and that provides atleast partial functionality to that device or device component.Depending on the particular device or device component, a functionallayer can include a broad range of compositions. For example, a devicethat is a solar array can be made from a starting functional layer ofIII-V micro solar cells, including a functional layer that is itselfmade up a plurality of distinct layers as provided herein. In certainembodiments, release and subsequent printing of such layers provides thebasis for constructing a photovoltaic device or device component. Incontrast, a functional layer for incorporation into electronics(MESFETs), LEDs, or optical systems may have a different layeringconfiguration and/or compositions. Accordingly, the specific functionallayer incorporated into the multilayer structure depends on the finaldevice or device component in which the functional layer will beincorporated.

“Release layer” (sometimes referred to as “sacrificial layer”) refers toa layer that at least partially separates one or more functional layers.A release layer is capable of being removed or providing other means forfacilitating separation of the functional layer from other layers of themulti-layer structure, such as by a release layer that physicallyseparates in response to a physical, thermal, chemical and/orelectromagnetic stimulation, for example. Accordingly, the actualrelease layer composition is selected to best match the means by whichseparation will be provided. Means for separating is by any one or moreseparating means known in the art, such as by interface failure or byrelease layer sacrifice. A release layer may itself remain connected toa functional layer, such as a functional layer that remains attached tothe remaining portion of the multilayer structure, or a functional layerthat is separated from the remaining portion of the multilayerstructure. The release layer is optionally subsequently separated and/orremoved from the functional layer.

“Buffer layer” refers to a layer of a device or device component whichis useful for protecting other layers of the device component. In oneembodiment, a buffer layer protects another device layer from etching.In an embodiment, a buffer layer does not impact or has a minimal impacton the function of the device. In one embodiment, an etch block layer isa buffer layer.

“Release” and “releasing” refer to at least partially separating twolayers, devices or device components from one another, for example bymechanical or physical separation, or by removal of at least a portionof one layer, device or device component. In some embodiments, removalof a sacrificial layer results in the release of a layer, device ordevice component. In some embodiments, layers, devices or devicecomponents are released by etching away a portion of the layer, deviceor device component. In certain embodiments, released components remainattached to the object with they are released from by one or moreanchors. In some embodiments, released components are subsequentlyattached to the object they are released from by one or more anchors.

“Etch” and “etching” refer to a process by which a portion of a layer,device or device component is reacted away, dissolved or otherwiseremoved. In embodiments, an anisotropic etch or a directional etchrefers to an etching process which preferentially removes material alonga specific direction. In embodiments, a wet etch refers to removal ofmaterial by exposure to a solution. In embodiments, a selective etchrefers to removal of a specific material or class of materials. Inembodiments, a reactive ion etch or an inductively coupled plasmareactive ion etch refers to an etching method which utilizes a plasma toetch away material, for example by reaction with ions in the plasma. Theterm “etchant” is used in the present description to broadly refer to asubstance which is useful for removal of material by etching. The term“electrochemical etching” refers to an etching process which utilizes anapplied electric potential, electric field or electric current. The term“photoelectrochemical etching” refers to an etching process whichutilizes an applied electric potential, electric field or electriccurrent and exposure to electromagnetic radiation.

An “etch mask” refers to material useful for preventing underlyingmaterial from being etched. In some embodiments, a thick etch maskrefers to an etch mask of a sufficient thickness that the majority ofthe mask remains after an etching process. In embodiments a thick etchmask has a thickness selected over the range of 100 nm to 5 μm. In someembodiments a metal etch mask refers to an etch block layer.

The term “mask” refers to a material which covers or otherwise blocksportions of an underlying material. Use of the term “mask” is intendedto be consistent with use of the term in the art of microfabrication. Inembodiments, the term “mask” refers to an etch mask, an optical mask, adeposition mask or any combination of these.

The terms “masked region” and “exposed region” respectively refer toportions of an underlying material which are blocked and unblocked by amask.

“Epitaxial regrowth” and “epitaxial growth” refers to a method ofgrowing crystalline layer by deposition of material, for example gas orliquid phase deposition. The term “epilayer” refers to a layer grown viaepitaxial growth.

The term “patterning” is used herein as in the art of microfabricationto broadly refer to a process by which portions of a layer, device ordevice component are selectively removed or deposited to create aspecified structure.

“Supported by a substrate” refers to a structure that is present atleast partially on a substrate surface or present at least partially onone or more intermediate structures positioned between the structure andthe substrate surface. The term “supported by a substrate” may alsorefer to structures partially or fully embedded in a substrate.

“Printable electronic device” or “printable electronic device component”refer to devices and structures that are configured for assembly and/orintegration onto substrate surfaces, for example by using dry transfercontact printing and/or solution printing methods. In embodiments, aprintable electronic device component is a printable semiconductorelement. In embodiments, printable semiconductor elements are unitarysingle crystalline, polycrystalline or microcrystalline inorganicsemiconductor structures. In various embodiments, printablesemiconductor elements are connected to a substrate, such as a motherwafer, via one or more bridge or anchor elements. In this context ofthis description, a unitary structure is a monolithic element havingfeatures that are mechanically connected. Semiconductor elements ofvarious embodiments may be undoped or doped, may have a selected spatialdistribution of dopants and may be doped with a plurality of differentdopant materials, including p- and n-type dopants. Certainmicrostructured printable semiconductor elements include those having atleast one cross sectional dimension greater than or equal to about 1micron and nanostructured printable semiconductor elements having atleast one cross sectional dimension less than or equal to about 1micron.

Printable semiconductor elements useful for a variety of applicationscomprise elements derived from “top down” processing of high purity bulkmaterials, such as high purity crystalline semiconductor wafersgenerated using conventional high temperature processing techniques. Inan embodiment, a printable semiconductor element comprises a compositeheterogeneous structure having a semiconductor operationally connectedto or otherwise integrated with at least one additional device componentor structure, such as a conducting layer, dielectric layer, electrode,additional semiconductor structure or any combination of these. In somemethods and systems of the present invention, the printablesemiconductor element(s) comprises a semiconductor structure integratedwith at least one additional structure selected from the groupconsisting of: another semiconductor structure; a dielectric structure;conductive structure, and an optical structure (e.g., optical coatings,reflectors, windows, optical filter, collecting, diffusing orconcentration optic etc.). In some embodiments a printable semiconductorelement comprises a semiconductor structure integrated with at least oneelectronic device component selected from the group consisting of: anelectrode, a dielectric layer, an optical coating, a metal contact pad asemiconductor channel. In some embodiments, printable semiconductorelements comprise stretchable semiconductor elements, bendablesemiconductor elements and/or heterogeneous semiconductor elements(e.g., semiconductor structures integrated with one or more additionalmaterials such as dielectrics, other semiconductors, conductors,ceramics etc.). Printable semiconductor elements include printablesemiconductor devices and components thereof, including but not limitedto printable LEDs, lasers, solar cells, p-n junctions, photovoltaics,photodiodes, diodes, transistors, integrated circuits, and sensors.

“Electronic device component” refers to a printable semiconductor orelectrical device. Exemplary electronic device component embodiments areconfigured for performing a function, for example emittingelectromagnetic radiation or converting electromagnetic radiation intoelectrical energy. In specific embodiments, multiple electronic devicecomponents are electrically interconnected and perform a more complextask or function than the individual device components perform alone.Useful electronic device components include, but are not limited to P-Njunctions, thin film transistors, single junction solar cells,multi-junction solar cells, photodiodes, light emitting diodes, lasers,CMOS devices, MOSFET devices, MESFET devices, photovoltaic cells,microelectricalmechanical devices and HEMT devices.

“Vertical type LED” refers to a light emitting diode device in which thefunctional components or layers of the device are arranged in a stackedconfiguration and the electrical contacts are made at the top and bottomof the stack.

“Solution printing” is intended to refer to processes whereby one ormore structures, such as transferable or printable elements, aredispersed into a carrier medium and delivered in a concerted manner toselected regions of a substrate surface. In an exemplary solutionprinting method, delivery of structures to selected regions of asubstrate surface is achieved by methods that are independent of themorphology and/or physical characteristics of the substrate surfaceundergoing patterning. Solution printing methods include, but are notlimited to, ink jet printing, thermal transfer printing, and capillaryaction printing.

“Contact printing” refers broadly to a dry transfer contact printingmethod such as with a stamp that facilitates transfer of features from astamp surface to a substrate surface. In an embodiment, the stamp is anelastomeric stamp. Alternatively, the transfer can be directly to atarget (e.g., device) substrate or host substrate. The followingreferences relate to self assembly techniques which may be used inmethods of the present invention to transfer, assembly and interconnecttransferable semiconductor elements via contact printing and/or solutionprinting techniques and are incorporated by reference in theirentireties herein: (1) “Guided molecular self-assembly: a review ofrecent efforts”, Jiyun C Huie Smart Mater. Struct. (2003) 12, 264-271;(2) “Large-Scale Hierarchical Organization of Nanowire Arrays forIntegrated Nanosystems”, Whang, D.; Jin, S.; Wu, Y.; Lieber, C. M. NanoLett. (2003) 3(9), 1255-1259; (3) “Directed Assembly of One-DimensionalNanostructures into Functional Networks”, Yu Huang, Xiangfeng Duan,Qingqiao Wei, and Charles M. Lieber, Science (2001) 291, 630-633; and(4) “Electric-field assisted assembly and alignment of metallicnanowires”, Peter A. Smith et al., Appl. Phys. Lett. (2000) 77(9),1399-1401.

Useful contact printing methods for assembling, organizing and/orintegrating transferable elements include dry transfer contact printing,microcontact or nanocontact printing, microtransfer or nanotransferprinting and self assembly assisted printing. Use of contact printing isbeneficial because it allows assembly and integration of a plurality oftransferable semiconductor in selected orientations and positionsrelative to each other. Contact printing also enables effectivetransfer, assembly and integration of diverse classes of materials andstructures, including semiconductors (e.g., inorganic semiconductors,single crystalline semiconductors, organic semiconductors, carbonnanomaterials etc.), dielectrics, and conductors. Contact printingmethods optionally provide high precision registered transfer andassembly of transferable semiconductor elements in preselected positionsand spatial orientations relative to one or more device componentsprepatterned on a device substrate. Contact printing is also compatiblewith a wide range of substrate types, including conventional rigid orsemi-rigid substrates such as glasses, ceramics and metals, andsubstrates having physical and mechanical properties attractive forspecific applications, such as flexible substrates, bendable substrates,shapeable substrates, conformable substrates and/or stretchablesubstrates. Contact printing assembly of transferable structures iscompatible, for example, with low temperature processing (e.g., lessthan or equal to 298K). This attribute allows the present opticalsystems to be implemented using a range of substrate materials includingthose that decompose or degrade at high temperatures, such as polymerand plastic substrates. Contact printing transfer, assembly andintegration of device elements is also beneficial because it can beimplemented via low cost and high-throughput printing techniques andsystems, such as roll-to-roll printing and flexographic printing methodsand systems.

“Stretchable” refers to the ability of a material, structure, device ordevice component to be strained without undergoing fracture. In anexemplary embodiment, a stretchable material, structure, device ordevice component may undergo strain larger than about 0.5% withoutfracturing, preferably for some applications strain larger than about 1%without fracturing and more preferably for some applications strainlarger than about 3% without fracturing.

The terms “flexible” and “bendable” are used synonymously in the presentdescription and refer to the ability of a material, structure, device ordevice component to be deformed into a curved shape without undergoing atransformation that introduces significant strain, such as straincharacterizing the failure point of a material, structure, device ordevice component. In an exemplary embodiment, a flexible material,structure, device or device component may be deformed into a curvedshape without introducing strain larger than or equal to about 5%,preferably for some applications larger than or equal to about 1%, andmore preferably for some applications larger than or equal to about0.5%.

“Semiconductor” refers to any material that is an insulator at very lowtemperatures, but which has an appreciable electrical conductivity at atemperatures of about 300 Kelvin. In the present description, use of theterm semiconductor is intended to be consistent with use of this term inthe art of microelectronics and electrical devices. Usefulsemiconductors include element semiconductors, such as silicon,germanium and diamond, and compound semiconductors, such as group IVcompound semiconductors such as SiC and SiGe, group III-V semiconductorssuch as AlSb, AlAs, Aln, AlP, BN, GaSb, GaAs, GaN, GaP, InSb, InAs, InN,and InP, group III-V ternary semiconductors alloys such as AlxGal-xAs,group II-VI semiconductors such as CsSe, CdS, CdTe, ZnO, ZnSe, ZnS, andZnTe, group I-VII semiconductors CuCI, group IV-VI semiconductors suchas PbS, PbTe and SnS, layer semiconductors such as PbI₂, MoS₂ and GaSe,oxide semiconductors such as CuO and Cu₂O.

The term semiconductor includes intrinsic semiconductors and extrinsicsemiconductors that are doped with one or more selected materials,including semiconductor having p-type doping materials (also known asP-type or p-doped semiconductor) and n-type doping materials (also knownas N-type or n-doped semiconductor), to provide beneficial electricalproperties useful for a given application or device. The termsemiconductor includes composite materials comprising a mixture ofsemiconductors and/or dopants. Useful specific semiconductor materialsinclude, but are not limited to, Si, Ge, SiC, AlP, AlAs, AlSb, GaN, GaP,GaAs, GaSb, InP, InAs, GaSb, InP, InAs, InSb, ZnO, ZnSe, ZnTe, CdS,CdSe, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, PbS, PbSe, PbTe, AlGaAs, AlInAs,AlInP, GaAsP, GaInAs, GaInP, AlGaAsSb, AlGaInP, and GaInAsP. Poroussilicon semiconductor materials are useful in the field of sensors andlight emitting materials, such as light emitting diodes (LEDs) and solidstate lasers. Impurities of semiconductor materials are atoms, elements,ions and/or molecules other than the semiconductor material(s)themselves or any dopants provided to the semiconductor material.Impurities are undesirable materials present in semiconductor materialswhich may negatively impact the electrical properties of semiconductormaterials, and include but are not limited to oxygen, carbon, and metalsincluding heavy metals. Heavy metal impurities include, but are notlimited to, the group of elements between copper and lead on theperiodic table, calcium, sodium, and all ions, compounds and/orcomplexes thereof.

In certain embodiments, the term “orientation” refers to a specificplane of a crystal structure, for example a semiconductor crystal. Incertain embodiments, the term “direction” refers to a specific axis, orequivalent axes, of a crystal structure. In embodiments, use of theterms orientation and direction with a specific numeric indicator isintended to be consistent with use in the fields of crystallography andmicrofabrication.

“Quantum well” refers to an active layer of a light emitting diodedevice. In one embodiment, a quantum well is a layer of an LED devicehaving a relatively narrow bandgap, surrounded on two sides by layershaving a relatively wider bandgap. “Barrier layer” refers to a layer ofa light emitting diode device which is positioned adjacent to a quantumwell layer and has a larger bandgap than the quantum well material. Inone embodiment, a quantum well layer is sandwiched between two barrierlayers. In another embodiment, multiple quantum well layers aresandwiched between multiple barrier layers.

“Contact layer” refers to refers to a layer of a light emitting diodedevice, for example used to make electrical contact with externalcircuit components, such as electrical interconnects. “Spreader layer”refers to a layer of a light emitting diode device, for example usefulfor providing voltage or current from a contact layer across the area ofa light emitting diode device. “Cladding layer” refers to a layer of alight emitting diode device, for example a layer surrounding the barrierlayer and quantum well layer.

“Good electronic performance” and “high performance” are usedsynonymously in the present description and refer to devices and devicecomponents have electronic characteristics, such as field effectmobilities, threshold voltages and on-off ratios, providing a desiredfunctionality, such as electronic signal switching and/or amplification.Exemplary printable elements exhibiting good electronic performance mayhave intrinsic field effect mobilities greater than or equal 100 cm² V⁻¹s⁻¹, and for some applications, greater than or equal to about 300 cm²V⁻¹ s⁻¹. Exemplary transistors exhibiting good electronic performancemay have device field effect mobilities great than or equal to about 100cm² V⁻¹ s⁻¹, for some applications, greater than or equal to about 300cm² V⁻¹ s⁻¹, and for other applications, greater than or equal to about800 cm² V⁻¹ s⁻¹. Exemplary transistors of exhibiting good electronicperformance may have threshold voltages less than about 5 volts and/oron-off ratios greater than about 1×10⁴.

“Plastic” refers to any synthetic or naturally occurring material orcombination of materials that can be molded or shaped, generally whenheated, and hardened into a desired shape. Useful plastics include, butare not limited to, polymers, resins and cellulose derivatives. In thepresent description, the term plastic is intended to include compositeplastic materials comprising one or more plastics with one or moreadditives, such as structural enhancers, fillers, fibers, plasticizers,stabilizers or additives which may provide desired chemical or physicalproperties.

“Prepolymer” refers to a material which is a polymer precursor and/or amaterial which, when cured, is a polymer. A “liquid prepolymer” refersto a prepolymer which exhibits one or more properties of a liquid, forexample flow properties. Specific prepolymers include, but are notlimited to, photocurable polymers, thermally curable polymers andphotocurable polyurethanes.

“Curing” refers to a process by which a material is transformed suchthat the transformed material exhibits one or more properties differentfrom the original, non-transformed material. In some embodiments, acuring process allows a material to become solid or rigid. In anembodiment, curing transforms a prepolymer material into a polymermaterial. Useful curing processes include, but are not limited to,exposure to electromagnetic radiation (photocuring processes), forexample exposure to electromagnetic radiation of a specific wavelengthor wavelength range (e.g., ultraviolet or infrared electromagneticradiation); thermal curing processes, for example heating to a specifictemperature or within a specific temperature range (e.g., 150° C. orbetween 125 and 175° C.); temporal curing processes, for example waitingfor a specified time or time duration (e.g., 5 minutes or between 10 and20 hours); drying processes, for example removal of all or a percentageof water or other solvent molecules; and any combination of these. Forexample, one embodiment for curing a silver epoxy comprises heating thesilver epoxy to 150° C. for a duration of 5 minutes.

“Polymer” refers to a molecule comprising a plurality of repeatingchemical groups, typically referred to as monomers. Polymers are oftencharacterized by high molecular masses. Useful polymers include organicpolymers and inorganic polymers, both of which may be in amorphous,semi-amorphous, crystalline or partially crystalline states. Polymersmay comprise monomers having the same chemical composition or maycomprise a plurality of monomers having different chemical compositions,such as a copolymer. Cross linked polymers having linked monomer chainsare also useful for some embodiments. Useful polymers include, but arenot limited to, plastics, elastomers, thermoplastic elastomers,elastoplastics, thermostats, thermoplastics and acrylates. Exemplarypolymers include, but are not limited to, acetal polymers, biodegradablepolymers, cellulosic polymers, fluoropolymers, nylons, polyacrylonitrilepolymers, polyamide-imide polymers, polyimides, polyarylates,polybenzimidazole, polybutylene, polycarbonate, polyesters,polyetherimide, polyethylene, polyethylene copolymers and modifiedpolyethylenes, polyketones, poly(methyl methacrylate, polymethylpentene,polyphenylene oxides and polyphenylene sulfides, polyphthalamide,polypropylene, polyurethanes, styrenic resins, sulfone based resins,vinyl-based resins or any combinations of these.

“Elastomer” refers to a polymeric material which can be stretched ordeformed and return to its original shape without substantial permanentdeformation. Elastomers commonly undergo substantially elasticdeformations. Useful elastomers may comprise polymers, copolymers,composite materials or mixtures of polymers and copolymers. Anelastomeric layer refers to a layer comprising at least one elastomer.Elastomeric layers may also include dopants and other non-elastomericmaterials. Useful elastomer embodiments include, but are not limited to,thermoplastic elastomers, styrenic materials, olefenic materials,polyolefin, polyurethane thermoplastic elastomers, polyamides, syntheticrubbers, PDMS, polybutadiene, polyisobutylene,poly(styrene-butadiene-styrene), polyurethanes, polychloroprene andsilicones.

“Transfer device” or “transfer substrate” refers to a substrate, deviceor device component capable of and/or configured for receiving and/orrelocating an element or array of elements, such as printable elements.Useful transfer devices include conformal transfer devices, such asdevices having one or more contact surfaces capable of establishingconformal contact with elements undergoing transfer. An elastomericstamp and/or transfer device is useful with a variety of the methods anddevices described herein. Useful elastomeric transfer devices include,but are not limited to, elastomeric stamps, composite elastomericstamps, an elastomeric layer, a plurality of elastomeric layers and anelastomeric layer coupled to a substrate such as a glass, ceramic, metalor polymer substrate.

“Target substrate” is used broadly to refer to the desired finalsubstrate that will support the transferred structure. In an embodiment,the target substrate is a device substrate. In an embodiment, the targetsubstrate is a device component or element that is itself supported by asubstrate.

“Large area” refers to an area, such as the area of a receiving surfaceof a substrate used for device fabrication, greater than or equal toabout 36 square inches.

“Pre-metalized” refers to a structure which includes metallic layers,components or features.

“Pre-patterned” refers to a structure which includes one or moredevices, components or relief features.

“Optical communication” refers to a configuration of two or moreelements wherein one or more beams of electromagnetic radiation arecapable of propagating from one element to the other element. Elementsin optical communication may be in direct optical communication orindirect optical communication. “Direct optical communication” refers toa configuration of two or more elements wherein one or more beams ofelectromagnetic radiation propagate directly from a first device elementto another without use of optical components for steering and/orcombining the beams. “Indirect optical communication” refers to aconfiguration of two or more elements wherein one or more beams ofelectromagnetic radiation propagate between two elements via one or moredevice components including, but not limited to, wave guides, fiberoptic elements, reflectors, filters, prisms, lenses, gratings and anycombination of these device components.

“Electrical contact” and “electrical communication” refers to thearrangement of one or more objects such that an electric currentefficiently flows from one object to another. For example, in someembodiments, two objects having an electrical resistance between themless than 100Ω are considered in electrical communication with oneanother. An electrical contact can also refer to a component of a deviceor object used for establishing electrical communication with externaldevices or circuits, for example an electrical interconnection.

“Electrical resistivity” refers to a property of a materialcharacteristic of the resistance to flow of electrons through thematerial. In certain embodiments, the resistivity of a material (p) isrelated to the resistance (R) of a length of material (L) having aspecific cross sectional area (A), e.g., ρ=R×A/L.

“Electrical interconnection” and “electrical interconnect” refers to acomponent of an electrical device used for providing electricalcommunication between two or more device components. In someembodiments, an electrical interconnect is used to provide electricalcommunication between two device components spatially separated from oneanother, for example spatially separated by a distance greater than 50nm, for some applications greater than 100 nm, for other applicationsgreater than 1 μm, and for yet other applications greater than 50 μm.“Electrode contact” refers to a component of an electronic device ordevice component to which an electrical interconnect attaches orprovides electrical communication to or from.

“Embed” refers to a process by which one object or device is buried,conformally surrounded or otherwise placed or positioned within or belowthe surface another object, layer or material. “Encapsulate” refers tothe orientation of one structure such that it is entirely surrounded byone or more other structures. “Partially encapsulated” refers to theorientation of one structure such that it is partially surrounded by oneor more other structures.

“Replicate” refers to a process by which one or more relief features aretransferred and/or recreated during casting, molding, embedding, orembossing processes. Replicated features generally resemble the featuresthey originate from except that the replicated features represent thenegative of the original features; that is where the original featuresare raised features, the replicated features are recessed features andwhere the original features are recessed features, the replicatedfeatures are raised features.

“Relief feature” refers to portions of an object or layer exhibitingdifferences in elevation and slope between the higher and lower parts ofthe surface of a given area or portion of the object or layer. “Raisedfeatures” refer to relief features which extend above the surface oraverage surface level of an object or layer or relief features whichhave elevations higher than other portions of the surface of an objector layer. “Recessed feature” refer to relief features which extend belowthe surface or average surface level of an object or layer or relieffeatures which have elevations lower than other portions of the surfaceof an object or layer.

“Conformal contact” refers to contact established between surfaces,coated surfaces, and/or surfaces having materials deposited thereonwhich may be useful for transferring, assembling, organizing andintegrating structures (such as printable elements) on a substratesurface. In one aspect, conformal contact involves a macroscopicadaptation of one or more contact surfaces of a conformal transferdevice to the overall shape of a substrate surface or the surface of anobject such as a printable element. In another aspect, conformal contactinvolves a microscopic adaptation of one or more contact surfaces of aconformal transfer device to a substrate surface leading to an intimatecontact without voids. The term conformal contact is intended to beconsistent with use of this term in the art of soft lithography.Conformal contact may be established between one or more bare contactsurfaces of a conformal transfer device and a substrate surface.Alternatively, conformal contact may be established between one or morecoated contact surfaces, for example contact surfaces having a transfermaterial, printable element, device component, and/or device depositedthereon, of a conformal transfer device and a substrate surface.Alternatively, conformal contact may be established between one or morebare or coated contact surfaces of a conformal transfer device and asubstrate surface coated with a material such as a transfer material,solid photoresist layer, prepolymer layer, liquid, thin film or fluid.

“Bind” and “bond” refers to the physical attachment of one object toanother. Bind and bound can also refer the retention of one object onanother. In one embodiment an object can bind to another by establishinga force between the objects. In some embodiments, objects are bound toone another through use of an adhesion layer. In one embodiment, anadhesion layer refers to a layer used for establishing a bonding forcebetween two objects.

“Placement accuracy” refers to the ability of a transfer method ordevice to transfer a printable element, to a selected position, eitherrelative to the position of other device components, such as electrodes,or relative to a selected region of a receiving surface. “Good placementaccuracy” refers to methods and devices capable of transferring aprintable element to a selected position relative to another device ordevice component or relative to a selected region of a receiving surfacewith spatial deviations from the absolutely correct position less thanor equal to 50 microns, more preferably less than or equal to 20 micronsfor some applications and even more preferably less than or equal to 5microns for some applications. Methods and devices described hereininclude those comprising at least one printable element transferred withgood placement accuracy.

“Fidelity” refers to a measure of how well a selected pattern ofelements, such as a pattern of printable elements, is transferred to areceiving surface of a substrate. Good fidelity refers to transfer of aselected pattern of elements wherein the relative positions andorientations of individual elements are preserved during transfer, forexample wherein spatial deviations of individual elements from theirpositions in the selected pattern are less than or equal to 500nanometers, more preferably less than or equal to 100 nanometers.

“Undercut” refers to a structural configuration wherein the bottomsurfaces of an element, such as a printable element, bridge elementand/or anchor element, are at least partially detached from or not fixedto another structure, such as a mother wafer or bulk material. Entirelyundercut refers to a refers to a structural configuration wherein thebottom surfaces of an element, such as printable element, bridge elementand/or anchor element, is completely detached from another structure,such as a mother wafer or bulk material. Undercut structures may bepartially or entirely free standing structures. Undercut structures maybe partially or fully supported by another structure, such as a motherwafer or bulk material, that they are detached from. Undercut structuresmay be attached, affixed and/or connected to another structure, such asa wafer or other bulk material, at surfaces other than the bottomsurfaces.

“Anchor” refers to a structure useful for connecting or tethering onedevice or device component to another. “Anchoring” refers to a processresulting in the connection or tethering of one device or devicecomponent to another.

“Homogeneous anchoring” refers to an anchor that is an integral part ofthe functional layer. In general, methods of making transferableelements by homogenous anchoring systems is optionally by providing awafer, depositing a sacrificial layer on at least a portion of a wafersurface, defining semiconductor elements by any means known in the art,and defining anchor regions. The anchor regions correspond to specificregions of the semiconductor element. The anchor regions can correspondto a geometrical configuration of a semiconductor layer, e.g., anchorsdefined by relatively large surface areas and are connected totransferable elements by bridge or tether elements. Such geometryprovides a means for facilitating lift-off of specific non-anchoredregions for either single-layer or multi-layer embodiments.Alternatively, anchors correspond to semiconductor regions that areattached or connected to the underlying wafer. Removing the sacrificiallayer provides a means for removing or transferring semiconductorelements while the portion of semiconductor physically connected to theunderlying wafer remains.

“Heterogeneous anchoring” refers to an anchor that is not an integralpart of the functional layer, such as anchors that are made of adifferent material than the semiconductor layer or is made of the samematerial, but that is defined after the transferable semiconductorelements are placed in the system. One advantage of heterogeneousanchoring compared to homogeneous anchoring relates to better transferdefining strategies and further improvement to the effective useablewafer footprint. In the heterogeneous strategy embodiment, a wafer isprovided, the wafer is coated with a sacrificial layer, semiconductorelements are defined, and heterogeneous anchor elements are depositedthat anchor semiconductor regions. In an aspect, the anchor is a resistmaterial, such as a photoresist or SiN (silicon nitride), or othermaterial that has a degree of rigidity capable of anchoring andresisting a lift-off force that is not similarly resisted bynon-anchored regions. The anchor may span from the top-mostsemiconductor layer through underlying layers to the underlying wafersubstrate. Removal of sacrificial layer provides a means for removingunanchored regions while the anchored regions remain connected to thewafer, such as by contact transfer, for example. In another embodiment,for a multi-layer system, the anchor provides anchoring of a top layerto an underlying semiconductor layer. Alternatively, the anchoringsystem is for single-layer semiconductor layer systems.

“Carrier film” refers to a material that facilitates separation oflayers. The carrier film may be a layer of material, such as a metal ormetal-containing material positioned adjacent to a layer that is desiredto be removed. The carrier film may be a composite of materials,including incorporated or attached to a polymeric material orphotoresist material, wherein a lift-off force applied to the materialprovides release of the composite of materials from the underlying layer(such as a functional layer, for example).

“Dielectric” and “dielectric material” are used synonymously in thepresent description and refer to a substance that is highly resistant toflow of electric current. Useful dielectric materials include, but arenot limited to, SiO₂, Ta₂O₅, TiO₂, ZrO₂, Y₂O₃, Si₃N₄, STO, BST, PLZT,PMN, and PZT.

“Device field effect mobility” refers to the field effect mobility of anelectronic device, such as a transistor, as computed using outputcurrent data corresponding to the electronic device.

“Fill factor” refers to the percentage of the area between two elements,such as between two electrodes, that is occupied by a material, elementand/or device component. In one embodiment, two electrodes are providedin electrical contact with one or more printable semiconductor elementsthat provide a fill factor between first and second electrodes greaterthan or equal to 20%, preferably greater than or equal to 50% for someapplications and more preferably greater than or equal to 80% for someapplications.

“Collecting” and “concentrating”, as applied to optics and opticalcomponents, refers to the characteristic of optical components anddevice components that collect light from a first area, in some cases alarge area, and optionally direct that light to another area, in somecases a relatively smaller area. In the context of some embodiments,collecting and concentrating optical components and/or opticalcomponents are useful for light detection or power harvesting by printedsolar cells or photodiodes.

“Conductive material” refers to a substance or compound possessing anelectrical resistivity which is typical of or equivalent to that of ametal, for example copper, silver or aluminum. In embodiments, theelectrical resistivity of a conductive material is selected over therange of 1×10⁻¹° to 1×10⁻² Ω·cm. In the present description, use of theterm conductive material is intended to be consistent with use of thisterm in the art of electronic devices and electric circuits. Inembodiments, conductive materials are useful as electricalinterconnections and/or for providing electrical communication betweentwo devices. A “conductive paste” refers to a conductive materialcomprising a mixture which is generally soft and malleable. In someembodiments, cured conductive pastes lose their soft and malleablenature and generally exhibit properties of a solid or a monolithic body.Exemplary conductive pastes comprise metal micro- and/or nano-particles.Silver epoxy refers to a conductive paste comprising micro- and/or nanoparticles including metallic silver (Ag) and which, when cured, exhibitsa low electrical resistivity, for example an electrical resistivitylower than 1×10⁻⁵ Ω·cm or selected over the range of 1×10⁻¹⁰ to 1×10⁻⁵Ω·cm.

“Fill” and “filling” refer to a process of depositing a material into arecessed feature. In one embodiment, a recessed region is filled byscraping material across and into the recessed feature. A filling toolgenerally refers to a device for moving material into a recessedfeature. In an embodiment, a filling tool refers to a device forscraping material across and/or into a recessed region. In a specificembodiment, a filling tool comprises a layer or solid body of PDMS. Forcertain embodiments, a filling process is conceptually similar to ascreen printing process where a material is scraped across a recessedfeature by a tool or device having dimensions larger than the recessedfeature, thereby at least partially filling the recessed feature withthe material.

“Align” refers to a process by which two objects are arranged withrespect to one another. “Aligned off center” refers to a process bywhich the centers of two objects or two areas are arranged such that thetwo centers are not coincident with respect to one or more spatialdimensions. For certain embodiments, the term aligned off center refersto alignment of the center of two objects such that the centers of theobjects are spatially separated by a distance greater than 50 nm, forsome applications greater than 100 nm, for other applications greaterthan 1 μm, and for yet other applications greater than 50 μm.

“Young's modulus” refers to a mechanical property of a material, deviceor layer which refers to the ratio of stress to strain for a givensubstance. Young's modulus may be provided by the expression;

$E = {\frac{({stress})}{({strain})} = \left( {\frac{L_{0}}{\Delta \; L} \times \frac{F}{A}} \right)}$

where E is Young's modulus, L₀ is the equilibrium length, ΔL is thelength change under the applied stress, F is the force applied and A isthe area over which the force is applied. Young's modulus may also beexpressed in terms of Lame constants via the equation:

$E = \frac{\mu \left( {{3\; \lambda} + {2\; \mu}} \right)}{\lambda + \mu}$

where μ and λ are Lame constants. High Young's modulus (or “highmodulus”) and low Young's modulus (or “low modulus”) are relativedescriptors of the magnitude of Young's modulus in a give material,layer or device. In the present description, a High Young's modulus islarger than a low Young's modulus, about 10 times larger for someapplications, more preferably about 100 times larger for otherapplications and even more preferably about 1000 times larger for yetother applications.

Described herein are printable structures and methods for making,assembling and arranging electronic devices. A number of the methodsdescribed herein are useful for assembling electronic devices where oneor more device components are embedded in a polymer which is patternedduring the embedding process with trenches for electrical interconnectsbetween device components. Some methods described herein are useful forassembling electronic devices by printing methods, such as by drytransfer contact printing methods. Also described herein are GaN lightemitting diodes and methods for making and arranging GaN light emittingdiodes, for example for display or lighting systems.

FIG. 24 illustrates an exemplary embodiment of a method for assemblingan electronic device. First, one or more electronic device components2401 are provided. In this embodiment, the electronic device componentsare printable device components including electrode contacts 2402. Atransfer substrate is also provided with a patterned surface 2403. Inthis embodiment, the patterned surface contains features for contactingand retrieving the device components onto the transfer substrate. Thepatterned surface also contains raised features 2404 which represent theorientation and configuration of electrical interconnects to befabricated between some of the electronic device components.

Next, the patterned transfer substrate is brought into contact with theelectronic device components 2401, where they are retrieved onto thetransfer substrate. A host substrate having a prepolymer layer 2405thereon is then provided to receive the electronic device components2401. The patterned transfer substrate 2403 having the electronic devicecomponents 2401 thereon is brought into contact with the prepolymerlayer 2405. The electronic device components 2401 are embedded into theprepolymer layer 2405 and, during this step, the patterned surface ofthe transfer substrate 2403 is also brought into contact with theprepolymer layer 2405. The raised features 2404 of the patterned surfaceare also embedded into the prepolymer layer 2405, at least partially,after which the prepolymer layer 2405 is cured into a hardened polymerlayer 2406. As the prepolymer layer 2405 is cured, the embeddedelectronic device components are fixed into place within the polymer2406, and the raised features of the patterned transfer surface arereplicated as recessed features 2407 in the polymer layer 2406. Once thepolymer layer 2406 is cured, the patterned transfer substrate 2403 andthe polymer layer 2406 are separated and the electronic devicecomponents 2401 are retained in the polymer layer 2406. Further, thepolymer layer includes a number of recessed features 2407.

Next, the recessed features 2407 are filled with a conducting materialto form electrical interconnects 2408 between the electronic devicecomponents 2401. In one embodiment, a line of silver epoxy conductivepaste is provided on the surface of the polymer. The silver epoxy isthen filled into the recessed features by dragging a filling tool acrossthe surface of the polymer. Optionally, the filling tool is draggedacross the surface of the polymer multiple times and in multipledirections to fill the recessed features. If necessary or desired,additional silver epoxy can be provided on the surface and the draggingsteps repeated to ensure that the recessed features are filled to thedesired level. Once filled, the conductive paste is cured to form rigidelectrical interconnections.

The invention may be further understood by the following non-limitingexamples.

Example 1 Printed Assemblies of Inorganic Light-Emitting Diodes forDeformable and Semitransparent Displays

This example describes methods for creating microscale inorganiclight-emitting diodes (LEDs) and for assembling and interconnecting theminto unusual display and lighting systems. The LEDs use specializedepitaxial semiconductor layers that allow delineation and release oflarge collections of ultrathin devices. Diverse shapes are possible,with dimensions from micrometers to millimeters, in either flat or“wavy” configurations. Printing-based assembly methods can deposit thesedevices on substrates of glass, plastic, or rubber, in arbitrary spatiallayouts and over areas that can be much larger than those of the growthwafer. The thin geometries of these LEDs enable them to beinterconnected by conventional planar processing techniques. Displays,lighting elements, and related systems formed in this manner can offerinteresting mechanical and optical properties.

Display devices represent ubiquitous, central components of nearly allconsumer electronics technologies. Organic light emitting diodes (OLEDs)are rapidly emerging as an attractive alternative to backlit liquidcrystals due to their comparatively high refresh rates, contrast ratios,power efficiencies, and capacity for vibrant color rendering. Inorganiclight emitting diodes (ILEDs) can also form displays, with propertiessuch as brightness, lifetime, and efficiency that can exceed thosepossible with OLEDs. These displays exist, however, only inultralarge-area, low-resolution formats (square meters; billboarddisplays), limited by processing and assembly procedures that do notscale effectively to small (<˜200 μm by 200 μm), thin (<˜200 μm) lightemitters or to dense, high-pixel count arrays. An ability to replaceexisting methods for fabricating ILEDs (i.e., wafer sawing, serialpick-and-place, wire bonding, and packaging on a device-by-device basis)and for incorporating them into displays (i.e., robotic assembly intotiles followed by interconnection using large quantities of bulk wiring)with those that more closely resemble the planar, batch processing ofOLEDs greatly expands the application opportunities. Examples includenot only ILED displays for desktop monitors, home theater systems, andinstrumentation gauging, but also, when implemented in flexible orstretchable forms, wearable health monitors or diagnostics andbiomedical imaging devices. In microscale sizes, such ILEDs can alsoyield semitransparent displays, with the potential for bidirectionalemission characteristics, for vehicle navigation, heads-up displays, andrelated uses.

This example provides routes to create ultrathin, ultrasmall ILEDs inflat or “wavy” geometries and to assemble them into addressable arraysusing scalable processing techniques, on substrates ranging from glassto plastic and rubber. The strategy includes four components: (i)epitaxial semiconductor multilayers designed for lateral delineation andrelease from a source wafer to yield isolated arrays of ILEDs, each ofwhich remains tethered to the wafer by polymeric “breakaway” anchorstructures; (ii) printing techniques for manipulating the resultingILEDs in schemes that enable formation of large-scale arrays on foreignsubstrates and in arbitrary spatial layouts; (iii) planar processingmethods for establishing electrical interconnects to the devices, indirect or matrix addressable configurations; and (iv) integrationstrategies capable of yielding ILED displays in flexible or stretchableformats and with conventional, semitransparent, or bidirectionalemission characteristics. Certain aspects build on previously reportedprocedures for etching and manipulating epitaxial semiconductor layersand for fabricating flexible and stretchable electronics.

FIG. 1 presents aspects of the first two of the components. Theepitaxial semiconductor layers include AlInGaP quantum well structures(6-nm-thick In_(0.56)Ga_(0.44)P wells, with 6-nm-thick barriers ofAl_(0.25)Ga_(0.26)In_(0.5)P on top and bottom), cladding films (200-nmthick layers of In_(0.5)Al_(0.5)P:Zn and In_(0.5)Al_(0.5)P:Si for the pand n sides, respectively), spreaders (800-nm-thick layers ofAl_(0.45)Ga_(0.55)As:C and Al_(0.45)Ga_(0.55)As:Si for the p and nsides, respectively), and contacts (5-nm-thick layer of GaAs:C and500-nm-thick layer of GaAs:Si for the p and n sides, respectively), fora total thickness of ˜2.523 all grown on AlAs (1500-nm-thick layer ofAl_(0.96)Ga_(0.04)As:Si) on a GaAs substrate (FIG. 5). The AlAs can beremoved by etching with hydrofluoric (HF) acid, in procedures that donot alter the overlying layers or the underlying substrate. The processfor defining the ILEDs first involves forming a pattern of verticaltrenches through the epitaxial layers by inductively coupled plasmareactive ion etching through a mask of SiO₂ definedphotolithographically (FIG. 6). This step determines the lateralgeometries of the devices (FIG. 5). FIGS. 1, A and B, shows top andcross-sectional scanning electron microscope (SEM) images collectedafter this etching process for a representative case, where the deviceislands in FIG. 1 are 50 μm by 50 Creating a pattern of photoresistposts (i.e., “breakaway” anchors) located at two of the four corners ofeach island, followed by immersion in concentrated HF, leads to theundercut release of an organized array of ILEDs. The anchors hold thedevices in their lithographically defined locations to prevent liftoffinto the etching bath, even after complete undercut (FIG. 6). Next, anautomated printing tool (FIG. 7) brings a soft elastomeric stamp withfeatures of relief embossed onto its surface into aligned contact with aselected set of these ILEDs. Peeling the stamp away fractures thephotoresist anchors and leaves the devices adhered via Van der Waalsinteractions to the raised regions of relief. FIGS. 1, C and D, showsschematic illustrations of the printing process and an SEM image of anarray of anchored ILEDs on the source wafer after one cycle of printing(FIG. 8). The white arrows in FIG. 1D highlight the collection of ILEDsremoved by this process, corresponding to every third device along thetwo orthogonal axes of the square array. FIG. 1E provides an SEM imageof these devices printed onto a glass substrate. The engineering designof the breakaway anchors is such that they are sufficiently robust tohold the ILEDs in their lithographically defined locations during theundercut etching and drying processes but sufficiently fragile to enablehigh-yield liftoff during printing. Three design aspects are the use of(i) a pair of anchors on the same side of each ILED, to yield, afterundercut, suspended, “diving board” layouts (FIG. 1F) that enabletransfer of torques large enough to fracture the photoresist uponpeel-back of the stamp; (ii) stamps with relief structures that areslightly smaller than the ILEDs and are offset from the centers of thedevices to maximize these torques and also to minimize overlap with theanchors; and (iii) photoresist structures that fracture more readilythan the semiconductor material. This type of anchoring scheme (i.e.,heterogeneous anchoring) is much more efficient in active materialsutilization and versatile in design choices than corresponding methodsdemonstrated previously for transistors and solar cells, whereperipheral parts of the devices themselves serve as the anchors (i.e.,homogeneous anchoring). Conventional wafer dicing and pick-and-placemethods are not suitable for devices with the thicknesses and dimensionsin the range reported here, due to challenges associated with waferutilization, device fragility, and size. Such techniques also lack thehigh-throughput, parallel operation of the type of printing methodsdescribed above.

FIG. 1G shows a micrograph of a densely packed array of anchored,undercut ILEDs on a source wafer. FIG. 1H shows sparse assemblies ofthese devices formed by printing in a step-and-repeat fashion from thiswafer to a glass substrate, coated with a thin (˜10 mm) layer ofpoly(dimethylsiloxane) (PDMS) to promote dry, conformal adhesion. Asexamples of high yields, large areas, and compatibility with plasticsubstrates, FIG. 1I presents images of collections of ILEDs printed ontoa thin sheet of polyethylene terephthalate (PET, 50 μm thick), shown aswrapped around a cylindrical glass support (1600 devices, in a squarearray with pitch of 1.4 mm; radius of cylinder ˜25 mm) and onto a plateof glass (inset; 1600 devices, in a square array with pitch of 1.4 mm).The overall fabrication yields, including delineation and undercut ofthe ILEDs and subsequent printing of them onto the target substrates,were 100% in both cases. The devices were selected to have sizes (i.e.,250 μm by 250 μm) large enough to be visible in the images; those withsizes of FIG. 1D are too small to be seen clearly at these scales.

Establishing electrical connections to these printed ILEDs yieldslighting elements or addressable displays. The small thickness (˜2.5 μm)of the devices enables the use of conventional thin-film processing,thereby providing a route to displays and related devices that issimpler, more scalable, and applicable to much smaller pixel geometriesthan established wire bonding and packaging techniques. To demonstratethe most basic scheme, we printed a collection of devices onto a thin,metal mesh on a transparent substrate, to form bottom contacts, and thenestablished separate top contacts using a planar lithographic process(FIG. 9). FIGS. 2, A and B, shows an exploded view schematicillustration and optical micrograph of an array of small, square devices(˜25 μm by 25 μm), as well as those with shapes that spell “LED.” Theresults indicate bright emission, even out to the edges of the devices,consistent with the relatively low surface recombination velocity inAlInGaP materials. For improved performance, ohmic contacts can beimplemented by using established metallization and annealing schemes.One strategy involves additional processing on the source wafer to yieldreleased devices with integrated ohmic contacts, suitable for printingand interconnection even on low-temperature substrates such as plasticor rubber. An alternative is to use low-temperature approaches toestablish the ohmics directly on such substrates. For this work, wepursued the second strategy, using processes that involve temperaturesbelow 175° C. (see FIG. 10 for transmission line model analysis of thecontact resistances). FIG. 2C shows the layout of an ILED with ohmiccontacts printed onto a thin layer of polyurethane on a glass substrate,and an optical micrograph of emission from a directly probed device.FIGS. 2, D and E, presents electrical and optical characteristics of aset of such devices, recorded on the wafer before undercut etching andafter printing. The processing in this case used a passivation scheme toeliminate moderate degradation in performance associated with the HFetching step on unprotected devices (FIG. 11). The resultingcurrent-voltage-emission behavior of the printed devices is comparableto that of the devices on the wafer. FIG. 3A provides a schematicillustration of an interconnect scheme for passive matrix addressing.Photolithography and electron beam evaporation define patterned metalelectrodes [Ti (20 nm)/Au (300 nm)] that connect p and n contacts(nonohmic for the cases of FIGS. 3 and 4) of devices in common columnsand rows, respectively. Two spin-cast, photopatterned layers of epoxy(1.2 μm thick) provide openings to these contacts; the top layerelectrically separates the column and row electrodes at their crossingpoints. Connecting terminal pads at the ends of these electrode lines toexternal computer control systems via ribbon cables that use anisotropicconductive films (ACFs) enables passive matrix addressing (see FIG. 12for details). FIG. 3B shows images of a small display that uses thisdesign, formed on a thin sheet of plastic (PET, 50 μm thick) with alayer of a photocurable polyurethane as an adhesive. The ILEDs havedimensions of 100 μm by 100 μm and are configured into a 16 by 16 squarearray. The yields on the individual pixels for the case of FIG. 3B are100%; at the level of the display, one column and two rows do notfunction, due to breaks in the contacts to the ACF ribbon cable [FIG.13; see FIG. 14 for an example of similar display with even smallerILEDs (50 μm by 50 μm)]. Such systems can be bent to radii of curvatureof ˜7 mm, with no observable degradation, even for several hundredcycles of bending (FIG. 14). Analytical calculation shows that even atthe minimum bend radius investigated here, the maximum strain in theILED is 0.21%, with a somewhat smaller strain (0.19%) in the quantumwell region. Analysis using literature parameters to determine thedependence of the bandgap on strain suggests changes in emissionwavelength of ˜2.4 nm for the smallest bend radius. As shown in FIG. 1,step-and-repeat printing can yield systems that cover areas much largerthan those of the constituent ILEDs or the source wafer. One importantoutcome is the ability to form displays that can offer an effectivelyhigh level of transparency, where only the ILEDs (and the electrodes, ifthey are not made with transparent conductors) are opaque. FIGS. 3, Cand D, shows examples of a 16 by 16 array, formed on glass. Here thearea of the display is ˜325 mm²; the cumulative area of all the ILEDs isonly ˜2.5 mm², corresponding to less than ˜1% of the display area. FIG.3C illustrates the operation of such a system positioned above a sheetof paper with printed logos; the focus of the image is on the paper,thereby illustrating a practical level of transparency for applicationin a heads-up display, for example. FIG. 3D shows the same device (lowerright), operating in front of a mirror (upper left) to demonstratebidirectional emission characteristics. The inset provides a magnifiedview of a region of this display, in its off state to show the smallsizes of the ILEDs compared to the unit cells. These layouts areimportant for many applications, due to the efficient utilization of theLED material, for reduced cost. For the examples shown, we achieved ˜98%yields on the individual devices, and ˜80% yields on theinterconnections, limited by breaks in the metal lines and failedcontacts to the ACF ribbon cable (FIG. 16).

The devices and integration methods reported here are compatible withstrategies to produce stretchable electronics, thereby providing a routeto conformable displays and lighting systems of the type that might beinteresting for integration with the human body and other curvilinear,deformable surfaces, all of which demand more than simple bending (e.g.,FIG. 3B). FIG. 4A shows an example of a stretchable ILED with the shapeof a ribbon. This device was formed by transfer printing and bonding toa prestrained, rubber substrate of PDMS. Relaxing the prestrain createsa device with a “wavy,” sinusoidal profile; this structure respondselastically to applied strain with a physics similar to that of anaccordion bellows to yield a stretchable ILED device. The top panelsprovide finite element simulation of the mechanics of the system incompressed (left) and stretched (right) configurations. The resultsindicate maximum strains in the ILED and the quantum well region of 0.36and 0.053%, respectively (see SOM for details). The bottom panels showoptical micrographs in the off (top) and on (bottom) states, with andwithout external illumination, respectively, in configurations similarto those illustrated in FIG. 22A. The emission characteristics show nonoticeable change in color with applied strain or associated changes indevice geometry from “wavy” to flat (see FIGS. 17 and 18 for details).This observation is consistent with a calculated change in emissionwavelength of less than ˜0.7 nm based on our computed strain values andanalysis similar to that performed for the flexible display.

The “wavy” strategy of FIG. 4A can accommodate only a relatively modestrange of applied strains (i.e., up to a few percent, for the designsreported here). A path to displays with high levels of stretchabilityuses non-coplanar mesh designs adapted from schemes reported forintegrated circuits. FIG. 4B presents optical micrographs of such asystem, composed of a 16 by 16 square array of ILEDs bonded to a PDMSsubstrate and interconnected by electrodes supported by arc-shapedbridges, with a fraction of the pixels turned on (overall yield >80%)(see FIG. 19 for details). The shapes of these bridges change inresponse to deformations of the display, in a way that isolates theILEDs from any significant strains (FIGS. 20 and 21). In particular,calculation shows that for strains of 24%, as defined by the change inseparation between inner edges of adjacent device islands, the maximumstrains in the ILED and quantum well are only 0.17 and 0.026%,respectively. The computed change in emission wavelength is less than˜0.3 nm. FIG. 4C provides optical micrographs of four pixels in thisdisplay, in their off and on states, with (top) and without (bottom)external illumination, respectively, in compressed and stretchedconfigurations. The images show the expected reduction in the heights ofthe arc-shaped bridges that lie in the direction of the applied tensileforce (i.e., along the interconnects that run from lower left to upperright), together with an increase in the heights of the bridges in theorthogonal direction, due to the Poisson effect. This mechanicalresponse is fully elastic—the bending-induced strains in theinterconnects are small, the strains in the ILEDs are negligible, andthe strain in the PDMS is well within its linear response regime. Thedata in FIGS. 4, D and E, are consistent with this mechanics, as are theassociated mechanics calculations. In particular, the current-voltagecharacteristics of a typical device do not change in a measurable wayfor applied strains up to ˜22%, and we observe no degradation on cyclingup to a few hundred times (500 times). Recent work demonstrates the useof smaller collections of large, conventional ILEDs in deformabledevices that use different designs.

The schemes reported here for creating thin, small inorganic LEDs andfor integrating them into display and lighting devices create designoptions that are unavailable with conventional procedures. The planarprocessing approaches for interconnect resemble those that are now usedfor organic devices and, for example, large-area electronics for liquidcrystal displays, thereby conferring onto inorganic LED technologiesmany of the associated practical advantages. In large area, high-pixelcount systems (e.g., 1 million pixels per square meter), the ability touse LEDs with sizes much smaller than those of the individual pixels isimportant to achieve efficient utilization of the epitaxialsemiconductor material, for reasonable cost. The minimum sizes ofdevices reported here are limited only by the resolution andregistration associated with manual tools for photolithography.

Materials and Methods

The materials and methods for this project, including epitaxialsemiconductor multilayer design, polymeric anchor structures, largescale printing techniques, and electrical interconnection in direct ormatrix addressable configurations, are described in the following, forthe flexible display, the large area display, the array of inorganiclight emitting diode (ILED) devices with ultrasmall sizes/arbitraryshapes, the wavy ribbon devices, and the stretchable display.

Preparation of ILEDs

FIG. 5 shows the epi-stack design for our ILEDs, capable of release froma source wafer by undercut etching, grown on a GaAs wafer (Epiworks,Inc.). The sequence of processing steps used to retrieve ILEDs arrayappears below. Polymeric anchor structures support the ILEDs duringundercut etching of the Al_(0.96)Ga_(0.04)As sacrificial layer (FIG. 6).

Processing Scheme for Preparing ILEDs from a Source Wafer

Delineating the ILEDs

1. Clean an epi-stack ILED wafer chip (acetone, isopropyl alcohol (IPA),deionized (DI) water).

2. Deposit 800 nm SiO₂ by plasma enhanced chemical vapor deposition(plasma enhanced chemical vapor deposition (PECVD); PlasmaTherm SLR).

3. Pretreat with hexamethyldisilazane (HMDS) for 1 min.

4. Pattern photoresist (PR; Clariant AZ5214, 3000 rpm, 30 sec) with 365nm optical lithography through an iron oxide mask (Karl Suss MJB3).Develop in aqueous base developer (Clariant AZ327 MIF) and bake on hotplate (110° C., 3 min).

5. Etch oxide with buffered oxide etchant (BOE; Fisher, 130 sec).

6. Etch with an inductively coupled plasma reactive ion etcher (ICP-RIE;Unaxis SLR 770 System, 2 mTorr, Cl₂ 4 sccm, H₂ 2 sccm, Ar 4 sccm, RF1:100 W, RF2: 500 W, ˜21 min).

Undercut Etching of the ILEDs

7. Clean the processed wafer chip from step 6 above with HF (Fisher,49%, diluted 10:1, 2 sec).

8. Pattern PR and bake at 110° C. for 5 min to form polymeric anchors atthe corners of the μ-ILEDs.

9. Dip the wafer chip in diluted HF (Fisher, 49%, diluted 100:1) for anappropriate time (μ-ILEDs with 50 μm×50 μm dimension: ˜4 hrs, 100μm×100-5.5 hrs) to remove the Al_(0.96)Ga_(0.04)As (sacrificial layer)underneath the ILEDs. Rinse by-product using DI water at 1.5 hrintervals.

Device Fabrication

Processing Scheme for ILED Devices of FIG. 2A; Schematic Illustration ofthese Steps Appears in FIG. 9.

Preparing a Substrate with Metal Mesh

1. Deposit 300 nm SiO₂ with PECVD onto a silicon wafer

2. Pretreat surface with HMDS for 1 min, and then pattern PR.

3. Deposit 7/70 nm of Cr/Au by electron beam evaporation.

4. Lift-off PR in acetone to yield a pattern of Cr/Au in the geometry ofa mesh.

5. Etch oxide with HF (49%, 38 sec).

6. Transfer print mesh to a glass substrate coated withpoly(dimethylsiloxane) (PDMS; Sylgard 184, Dow Corning, spun at 600rpm/5 sec, 3000 rpm/30 sec, cured in oven at 70° C. for 90 min) formedby mixing the base and curing agent with a ratio of 10:1 followed bythermal curing.

Printing the ILEDs

7. Liftoff ILEDs using a flat PDMS stamp formed by mixing the base andcuring agent with a ratio of 8.5:1.5, and then thermally cure.

8. Print ILEDs onto the glass substrate with Cr/Au mesh (n-contact).

9. Remove PR by washing in acetone.

Forming the interlayer and p-contact metallization

10. Spin coat the substrate from step 9 with a photodefinable epoxy(SU8-2, Microchem, spun at 1,500 rpm for 30 s). Soft bake at 65° C. and95° C. for 1 min and 1.5 min, respectively.

11. Pattern epoxy by exposing to ultraviolet (UV) light in a maskaligner for 14 sec, baking at 95° C. for 2 min, developing (SU8developer, Microchem) for 15 sec, rising (IPA), and curing (110° C., 35min, slow cooling).

12. Pattern PR.

13. Deposit 7 nm of Pd—Au by sputtering.

14. Lift-off PR in acetone to leave a thin layer of Pd—Au on the topsurfaces of the ILEDs (pcontact).

Processing Scheme for ILED Devices with Ohmic Contacts of FIG. 2C

Preparing the Substrate

1. Clean a glass slide (25 mm×25 mm) (acetone, IPA, DI water)

2. Expose to ultraviolet induced ozone (UVO) for 5 min.

3. Spin coat with polyurethane (NOA61; Norland Products Inc., spun at5000 rpm/60 sec).

Delineating the ILEDs

4. Clean an epi-stack ILED wafer chip (acetone, IPA, DI water).

5. Deposit 800 nm SiO₂ with PECVD.

6. Pretreat with HMDS for 1 min.

7. Pattern PR and bake on hot plate (110° C., 3 min).

8. Etch oxide with BOE (130 sec).

9. Etch with ICP-RIE (2 mTorr, Cl₂ 4 sccm, H₂ 2 sccm, Ar 4 sccm, RF1:100 W, RF2: 500 W, ˜16 min) to expose Al_(0.96)Ga_(0.04)As (sacrificiallayer) underneath the ILEDs.

Forming a passivation layer and undercut etching of the ILEDs

10. Clean the processed wafer chip from step 9 above (acetone, IPA, DIwater).

11. Spin coat with epoxy (SU8-2, spun at 3,000 rpm for 30 sec). Softbake at 65° C. and 110° C. each for 1 min and 1 min, respectively.

12. Pattern epoxy by exposing to UV, baking, developing, rising (IPA),and curing. The pattern includes a passivation structure to protectμ-ILEDs and an anchor structure to suspend ILEDs during the undercutetching.

13. Dip the wafer chip in diluted HF (49%, diluted 100:1) for ˜2 hrs toremove the Al_(0.96)Ga_(0.04)As (sacrificial layer) underneath theμ-ILEDs.

Printing the ILEDs

14. Liftoff ILEDs using a flat PDMS stamp formed by mixing the base andcuring agent with a ratio of 10:1, followed by thermal curing. Contact‘inked’ stamp against the substrate from step 13.

15. Retrieve the stamp after UV exposure (through the stamp) for 20 min.Cure the polyurethane layer by UV exposure for 2 hours.

Defining the n-contact regions

16. Reactive ion etch (RIE; PlasmaTherm 790 Series, 50 mTorr, 20 sccmO₂, 100 W, ˜12 min) to remove the epoxy on the top surface of the ILEDs.

17. Pattern PR and bake at 110° C. for 2 min.

18. Wet etch C-doped p-GaAs/p-spreader(Al_(0.45)Ga_(0.55)As) byH₃PO₄/H₂O₂/H₂O (volume ratio 1:13:12) for 25 sec, InGaP-based activeregion by HCl/H₂O (2:1) for 15 sec and Si-doped nspreader(Al_(0.45)Ga_(0.55)As) by H₃PO₄/H₂O₂/H₂O (1:13:12) for 23 sec to exposeSi-doped n-GaAs.

19. Remove PR by washing in acetone.

Defining the n-Ohmic Contact Metallization

20. Pattern PR.

21. Clean the surface of n-GaAs with HCl:DI water (1:1) for 30 sec.

22. Deposit 5/35/70 nm of Pd/Ge/Au by electron beam evaporation.

23. Lift-off PR in acetone to remain Pd/Ge/Au on the top surface ofn-GaAs.

24. Anneal at 175° C. for 60 min under N₂ ambient

Defining the p-Ohmic Contact Metallization

25. Pattern PR.

26. Clean the surface of p-GaAs with HCl:DI water (1:1) for 30 sec.

27. Deposit 10/40/10/70 nm of Pt/Ti/Pt/Au by electron beam evaporation.

28. Lift-off PR in acetone to remain Pt/Ti/Pt/Au on the top surface ofp-GaAs.

Processing Scheme for Flexible ILED Displays of FIG. 3B

Preparing the Substrate

1. Clean a glass slide (30 mm×30 mm) (acetone, IPA, DI water).

2. Treat with ultraviolet induced ozone (UVO) for 5 min.

3. Spin coat with PDMS (spun at 600 rpm/5 sec, 3000 rpm/30 sec), formedby mixing the base curing agent with a ratio of 10:1.

4. Cure PDMS in an oven (70° C., 90 min).

5. Clean a sheet of polyethylene terephthalate (PET; Grafix DURA-LAR, 32mm×32 mm×50 urn) (IPA, DI water).

6. Laminate the PET sheet onto the PDMS coated glass slide, as a carrierfor the following processing steps.

7. Spin coat with polyurethane (NOA61; Norland Products Inc., spun at5000 rpm/60 sec).

Printing the ILEDs

8. Liftoff an array of ILEDs (16×16 array of devices with dimensions of100 μm×100 μm) using a flat PDMS stamp. Contact ‘inked’ stamp againstthe substrate from step 7.

9. Retrieve the stamp after UV exposure (through the stamp) for 20 min.

10. Remove PR by washing in acetone and then cure the polyurethane layerby UV exposure for 2 hours.

Defining the n-Contact Regions

11. Reactive ion etch (RIE; PlasmaTherm 790 Series, 50 mTorr, 20 sccmO₂, 100 W, 8 min) to remove the polyurethane layer covering the ILEDs.

12. Pattern PR and bake at 110° C. for 2 min.

13. Wet etch C-doped p-GaAs/p-spreader(Al_(0.45)Ga_(0.55)As) byH₃PO₄/H₂O₂/H₂O (volume ratio 1:13:12) for 25 sec, InGaP-based activeregion by HCl/H₂O (2:1) for 15 sec and Si-doped nspreader (Al₀₄₅Ga₀₅₅As)by H₃PO₄/H₂O₂/H₂O (1:13:12) for 23 sec to expose Si-doped n-GaAs.

14. Remove PR by washing in acetone.

Defining the n-Contact Metallization

15. Spin coat with epoxy (SU8-2, spun at 3,000 rpm for 30 sec). Softbake at 65° C. and 110° C. each for 1 min and 1 min, respectively.

16. Pattern epoxy by exposing to UV, baking, developing, rising (IPA),and curing.

17. Deposit 20/300 nm of Ti/Au by electron beam evaporation.

18. Pattern PR and bake at 110° C. for 2 min.

19. Wet etch Ti/Au for 45/90 sec by BOE and Au etchant (Transene, Inc.).

20. Remove PR by washing in acetone.

Defining the p-Contacts and p-Contact Metallization

21. Spin coat with epoxy (SU8-2, spun at 3,000 rpm for 30 s). Soft bakeat 65° C. and 110° C. for 1 min and 1 min, respectively.

22. Pattern epoxy by exposing to UV, developing, rising, and curing.

23. Deposit 20/300 nm of Ti/Au by electron beam evaporation.

24. Pattern PR and bake at 110° C. for 2 min.

25. Wet etch Ti/Au for 45/90s by BOE and Au etchant.

26. Remove PR by washing in acetone.

Forming an Encapsulation Layer

27. Spin coat with epoxy (SU8-5, Microchem, spun at 3,000 rpm for 30 s).Soft bake at 65° C. and 110° C. for 1 min and 1.5 min, respectively.

28. Pattern epoxy by exposing to UV for 14 sec, baking at 95° C. for 2min, developing (SU8 developer) for 18 sec, rising (IPA), and curing(110° C., 35 min, slow cooling)

Processing Scheme for Large Area ILEDs Displays of FIGS. 3, C and D

Preparing the Substrate

1. Clean a glass slide (50 mm×50 mm) (acetone, IPA, DI water)

2. Deposit 50 nm of Ti by electron beam evaporation.

3. Pattern PR and bake on a hot plate (110° C., 2 min) to form guidelines to assist in registration of ILEDs printed with an automatedprinter system.

4. Wet etch Ti with BOE (70 sec).

5. Remove PR by washing in acetone.

6. Expose to ultraviolet induced ozone (UVO) for 15 min.

7. Spin coat with PDMS (spun at 600 rpm/5 sec, 2500 rpm/30 sec) formedby mixing the base and curing agent with a ratio of 10:1.

8. Cure PDMS in an oven (70° C., 90 min)

Printing the ILEDs

9. Selectively liftoff ILEDs (100 μm×100 μm lateral dimensions) using acomposite stamp in automated printing machine (FIGS. 7, 8) and printthem onto the substrate from step 8, in a step and repeat fashion toform a 16×16 array.

10. Remove PR by washing in acetone.

Patterning the p-Contact Metallization

11. Spin coat with epoxy (SU8-2, spun at 1,500 rpm for 30 s). Soft bakeat 65° C. and 110° C. for 1 min and 1 min, respectively.

12. Pattern epoxy by exposing to UV, baking, developing, rising, andcuring.

13. Deposit 10/70 nm of Ti/Au by electron beam evaporation.

14. Pattern PR and bake at 110° C. for 2 min.

15. Wet etch Ti/Au with BOE and gold etchant for 35/20 sec.

16. Remove PR by washing in acetone.

17. Reactive ion etch (RIE, 50 mTorr, 20 sccm O₂, 100 W, 13 min) toremove remaining epoxy around the sidewalls of the ILEDs (FIG. 12).

Defining the n-Contact Regions

18. Pattern PR and bake at 110° C. for 2 min.

19. Wet etch C-doped μ-GaAs/p-spreader by H₃PO₄/H₂O₂/H₂O (1:13:12) for25 sec, InGaP-based active region by HCl/H₂O (2:1) for 15 sec andSi-doped n-spreader by H₃PO₄/H₂O₂/H₂O (1:13:12) for 23 sec to exposeSi-doped n-GaAs.

20. Remove PR by washing in acetone.

Patterning the n-Contact Metallization

21. Spin coat with epoxy (SU8-2, spun at 3,000 rpm for 30 sec). Softbake at 65° C. and 110° C. for 1 min and 1 min, respectively.

22. Pattern epoxy by exposing to UV, baking, developing, rising, andcuring.

23. Deposit 20/300 nm of Ti/Au by electron beam evaporation.

24. Pattern PR and bake at 110° C. for 2 min.

25. Wet etch Ti/Au for 45/90 sec with BOE and Au etchant.

26. Remove PR by acetone rinse.

Defining the p-Contact Regions and Metallization

27. Spin coat with epoxy (SU8-2, spun at 3,000 rpm for 30 s). Soft bakeat 65° C. and 110° C. for 1 min and 1 min, respectively.

28. Pattern epoxy with exposing UV, developing, rising, and curing.

29. Deposit 20/300 nm of Ti/Au by electron beam evaporation.

30. Pattern PR and bake at 110° C. for 2 min.

31. Wet etch Ti/Au for 45/90s by BOE and Au etchant.

32. Remove PR by acetone.

Forming an Encapsulation Layer

33. Spin coat with epoxy (SU8-5, spun at 3,000 rpm for 30 s). Soft bakeat 65° C. and 110° C. for 1 min and 1.5 min, respectively.

34. Pattern epoxy by exposing to UV, baking, developing, rising, andcuring.

Processing Scheme for Stretchable ILEDs of FIG. 4A

Exploded view schematic illustration of the processing step appears inFIG. 18.

Preparing Ribbon Shaped ILEDs

1. Clean an epi-stack ILED wafer chip (acetone, IPA, DI water).

2. Pattern PR and bake for 2 min.

3. Wet etch C-doped p-GaAs/p-spreader by H₃PO₄/H₂O₂/H₂O (1:13:12) for 25sec, InGaP-based active region by HCl/H₂O (2:1) for 15 sec and Si-dopedn-spreader by H₃PO₄/H₂O₂/H₂O (1:13:12) for 35 sec to exposeAl_(0.06)Ga_(0.04)As (sacrificial layer) underneath the μ-ILEDs.

4. Remove PR by washing in acetone.

Forming an Encapsulation Layer and Undercut Etching

5. Pattern PR on the top surface of the ribbons.

6. Deposit 3/15 nm of Ti/Au by electron beam evaporation.

7. Lift-off PR in acetone to remain Ti/Au on the top surface of theribbons.

8. Spin coat with epoxy (SU8-2, spun at 3,000 rpm for 30 s). Soft bakeat 65° C. and 95° C. for 1 min and 1.5 min, respectively.

9. Pattern epoxy by exposing to UV, baking, developing, rising (IPA),and curing.

10. Dip the ILED in diluted HF (100:1) for 1 hr to release the ribbonsfrom the wafer.

11. Rinse in DI water for 5 min.

12. Print ribbons onto a pre-strained substrate of PDMS withprepatterned metal lines.

Processing Scheme for Stretchable ILED Display of FIGS. 4, B and C

Schematic illustration of the processing steps appears in FIG. 20.

Preparing the Carrier Substrate

1. Clean a glass slide (25 mm×25 mm) (acetone, IPA, DI water).

2. UVO treatment for 5 min.

3. Spin coat with PMMA (A2, Microchem, spun at 3,000 rpm for 30 sec).

4. Anneal at 180° C. for 3 min.

5. Spin coat with polyimide (PI, poly(pyromelliticdianhydride-co-4,4′-oxydianiline), amic acid solution, Sigma-Aldrich,spun at 4,000 rpm for 60 sec).

6. Anneal at 110° C. for 3 min and 150° C. for 10 min.

7. Anneal at 250° C. for 50 min in N₂ atmosphere.

8. Spin coat with epoxy (SU8-2, spun at 3,000 rpm for 30 sec). Soft bakeat 65° C. and 95° C. for 1 min and 1 min, respectively.

Printing the ILEDs

9. Liftoff ILEDs (16×16 array of devices with dimensions of 50 μm×50 μm)using a flat PDMS stamp and contact the ‘inked’ stamp with the substratefrom step 8.

10. Remove the stamp after UV exposure (through the stamp) for 60 secand baking at 110° C. for 10 min.

11. Remove PR by washing with acetone. Fully cure the epoxy layer at150° C. for 20 min.

Forming the Sidewall Region

12. Spin coat with epoxy (SU8-2, spun at 3,000 rpm for 30 sec). Softbake at 65° C. and 95° C. for 1 min and 1 min, respectively.

13. Expose to UV for 14 sec and bake at 110° C. for 1 min.

14. Anneal at 150° C. for 20 min.

15. Reactive ion etch (RIE; PlasmaTherm 790 Series, 50 mTorr, 20 sccmO₂, 100 W, 13 min) to remove remaining epoxy around the sidewalls of theILEDs.

Defining the n-Contact Regions

16. Pattern PR and bake at 110° C. for 5 min.

17. Wet etch C-doped p-GaAs/p-spreader by H₃PO₄/H₂O₂/H2O (1:13:12) for25 sec, InGaP-based active region by HCl/H₂O (2:1) for 15 sec andSi-doped n-spreader by H₃PO₄/H₂O₂/H₂O (1:13:12) for 23 sec to exposeSi-doped n-GaAs.

18. Remove PR by washing with acetone.

Defining the n- and p-Contact Metallization

19. Spin coat with epoxy (SU8-2, spun at 3,000 rpm for 30 s). Soft bakeat 65° C. and 95° C. for 1 min and 2 min, respectively.

20. Pattern epoxy by exposing to UV for 14 sec, developing for 15 sec,rising, and curing (110° C., 35 min, slow cooling).

21. Deposit 20/300 nm of Ti/Au by electron beam evaporation.

22. Pattern PR and bake at 110° C. for 2 min to define n-contactelectrodes, designed as line patterns connected to n-GaAs, and p-contactelectrodes, designed as line patterns that avoid crossing over then-contact electrodes (FIG. 20).

23. Wet etch Ti/Au for 45/90 sec by BOE and Au etchant.

24. Remove PR by washing with acetone.

Interconnecting the p-Contact Metallization

25. Spin coat with epoxy (SU8-2, spun at 3,000 rpm for 30 sec). Softbake at 65° C. and 95° C. for 1 min and 2 min, respectively.

26. Pattern epoxy by exposing to UV, developing, rising, and curing.

27. Deposit 20/300 nm of Ti/Au by electron beam evaporation.

28. Pattern PR and bake at 110° C. for 2 min.

29. Wet etch Ti/Au for 45/90 sec by BOE and Au etchant.

30. Remove PR by washing with acetone.

Forming and Encapsulation Layer

31. Spin coat with epoxy (SU8-2, spun at 3,000 rpm for 30 s). Soft bakeat 65° C. and 95° C. for 1 min and 1.5 min, respectively.

32. Pattern epoxy by exposing to UV, developing, rising, and curing.

Forming the Island/Bridge Structures

33. Deposit 150 nm SiO₂ by PECVD.

34. Pattern PR and bake at 110° C. for 2 min.

35. RIE (50 mTorr, CF₄/O₂ 40/1.2 sccm, 150 W, 8 min) to etch SiO₂.

36. RIE (150 mTorr, O₂ 20 sccm, 150 W, 50 min) to etch epoxy/PI layers.

37. Etch oxide with BOE (20 sec).

Transferring the Mesh

38. Immerse the ILEDs array mesh from step 37 in acetone (80° C.) for˜10 min to dissolve the PMMA.

39. Lift off the mesh using a PDMS stamp formed by mixing a base andagent with a ratio of 8.5:1.5.

40. Selectively deposit 5/30 nm of Ti/SiO₂ by electron beam evaporationon the bottom of island regions through a shadow mask.

41. Transfer the ILED mesh to a biaxially pre-strained PDMS substrate.

42. Anneal in an oven at 70° C. and release the strain.

Measurement of Emission Spectra

Emission spectra were measured using a spectrometer (Oceanoptics,HR4000) which enabled signal collected through an optical fiber directlymounted in an electrical probing station.

Measurement of Surface Profile of Wavy ILEDs

The wavelength and amplitude of stretchable ILEDs of FIG. 4A weremeasured by a surface profiler (Sloan Dektak3). A diamond stylus incontact with a sample surface scans along the length of ribbon andmeasures physical surface variation at different positions.

Bending Test

To evaluate the bending performance of flexible ILEDs displays, bendingtest were performed (FIGS. 16A, B). The displays were bent and released,with bend radii down to ˜7.3 mm. The electrical properties of 32different pixels in the display were measured and averaged to assess theperformance.

Fatigue Test

To evaluate the fatigue performance of flexible ILED displays, multiplecycling tests were performed under repetitive bending and releasing upto 500 times (FIG. 16C, D). Electrical measurements were performed on 16different pixels, for a bend radius of ˜8.8 mm. Stretching tests wereperformed with mechanical stages capable of applying uniaxial strain toevaluate the performance of stretchable ILED display under repetitivestretching and releasing up to 500 times (FIG. 4). Electrical propertiesof 14 different pixels in the display were measured and averaged. In allcases, the testing was performed at a rate of roughly one cycle persecond.

Modeling of Flexible ILED Displays of FIG. 3B

The encapsulation, electrode, ILED, adhesive and plastic shown in FIG.12 can be modeled as a composite beam subject to a bend curvature. Thedistance between the neutral mechanical plane and the top surface ineach cross section is given by

${\sum\limits_{i = 1}^{N}\; {{\overset{\_}{E}}_{i}{{h_{i}\left( {{\sum\limits_{j = 1}^{i}\; h_{j}} - \frac{h_{i}}{2}} \right)}/{\sum\limits_{i = 1}^{N}\; {{\overset{\_}{E}}_{i}h_{i}}}}}},$

where N is the total number of layers, h_(i) is the thickness of thei^(th) layer (from the top), and Ē_(i)h_(j)/1−v_(i) ² is related to theYoung's modulus E_(i) and Poisson's ratio v_(i) of the i^(th) layer. Thestrain in the μ-ILED, including the quantum well, is given by y/R, whereR is the bend radius, and y is the distance from the neutral mechanicalplane. The elastic properties and layer thicknesses used for bendabledisplay are (1) E_(encapsulation)=4.4 GPa, V_(encapsulation)=0.44, andh_(encapsulation1)=4.0 μm and h_(encapsulation2)=0.877 μm for the twoencapsulation layers above and below the electrode, respectively; (2)E_(electrode)=78 GPa, V_(electrode)=0.44, and h_(electrode)=300 nm; (3)E_(ILED)=77.5 GPa, V_(ILED)=0.312, and h_(ILED)=2.523 μm; (4)E_(adhesive)=1 GPa, V_(adhesive)=0.3, and h_(adhesive)=2.5 urn; and (5)E_(plastic)=4 GPa, V_(plastic)=0.44 and h_(plastic)=50 urn. These givethe neutral mechanical plane 19.76 urn below the top surface. Themaximum distance from the ILED is then 14.58 μm to the neutralmechanical plane, which gives the maximum strain 0.21% in the ILED forthe bend radius R=7 mm. The quantum well is 1.011 μm below the topsurface of ILED (FIG. 5), and is therefore 13.57 μm to the neutralmechanical plane. This gives the maximum strain 0.19% for the bentradius R 7 mm.

Modeling and Simulation of Stretchable ILEDs of FIG. 4A: The Wavy Design

As shown in FIG. 18A, the stretchable ILED consists of theencapsulation, electrode and μ-ILED and can be modeled as a compositebeam with the effective tensile stiffness

$\overset{\_}{EA} = {\sum\limits_{i = 1}^{3}\; {{\overset{\_}{E}}_{i}h_{i}}}$

and bending stiffness

${\overset{\_}{EI} = {{\sum\limits_{i = 1}^{3}\; {{\overset{\_}{E}}_{i}{h_{i}\left\lbrack {\left( {\sum\limits_{j = 1}^{i}\; h_{j}} \right)^{2} - {\left( {\sum\limits_{j = 1}^{i}\; h_{j}} \right)h_{i}} + \frac{h_{i}^{2}}{3}} \right\rbrack}}} - \frac{\left\lbrack {\sum\limits_{i = 1}^{3}\; {{\overset{\_}{E}}_{i}{h_{i}\left( {{\sum\limits_{j = 1}^{i}\; h_{j}} - \frac{h_{i}}{2}} \right)}}} \right\rbrack^{2}}{\overset{\_}{EA}}}},$

where the summation is for the 3 layers of encapsulation, electrode andILED, h_(i) is the thickness of the i^(th) layer (from the top), andĒ_(i)=E_(i)/(1−v_(i) ²) is related to the Young's modulus E_(i) andPoisson's ratio v_(i) of the i^(th) layer. The distance between theneutral mechanical plane and the top surface in each cross section isgiven by

$\sum\limits_{i = 1}^{3}\; {{\overset{\_}{E}}_{i}{{h_{i}\left( {{\sum\limits_{j = 1}^{i}h_{j}} - \frac{h_{i}}{2}} \right)}/{\overset{\_}{EA}.}}}$

The device was formed by transfer printing and bonding to a pre-strainedsubstrate of PDMS. Relaxing the pre-strain creates a device with a‘wave’ of the amplitude A and wavelength λ. The bending energy andmembrane energy of the wavy device are

$U_{bending} = \frac{4\; \pi^{4}\overset{\_}{EI}\; {LA}^{2}}{\lambda^{4}}$and${U_{membrane} = {\frac{1}{2}\overset{\_}{EA}{L\left\lbrack {{\pi^{2}\left( \frac{A}{\lambda} \right)}^{2} + ɛ_{pre}} \right\rbrack}^{2}}},$

where L is the length of device and ∈_(pre) (<0) is the compressivestrain on the device upon the release of the pre-strain in the PDMS.

The strain energy in the PDMS substrate due to the sinusoidaldisplacement profile on its top surface is

${U_{substrate} = {{\overset{\_}{E}}_{s}L\frac{\pi \; A^{2}}{4\; \lambda}}},$

where Ē_(s)=E_(s)/(1−v_(s) ²) is related to the Young's modulus E_(s)and Poisson's ratio v_(s) of the PDMS substrate. The minimization of thetotal energy U_(total)=U_(bending)+U_(membrane)+U_(substrate) givesanalytically the wave length and amplitude as

$\begin{matrix}{{\lambda = {2\; {\pi \left( \frac{4\; \overset{\_}{EI}}{{\overset{\_}{E}}_{s}} \right)}^{1/3}}},} & (1) \\{{A = {\frac{\lambda}{\pi}\sqrt{{ɛ_{pre}} - ɛ_{crit}}}},} & (2)\end{matrix}$

where

$ɛ_{crit} = {\frac{3}{2}\left\lbrack \frac{\overset{\_}{EI}{\overset{\_}{E}}_{s}^{2}}{2\left( \overset{\_}{EA} \right)^{3}} \right\rbrack}^{1/3}$

is the critical strain for buckling.

The strain in the ILED, including the quantum well, is given by

${4\; \pi^{2}\frac{A}{\lambda^{2}}y},$

where y is the distance from the neutral mechanical plane. The elasticproperties and layer thicknesses used for the device are (1)E_(encapsulation)=4.4 GPa, V_(encapsulation)=0.44, andh_(encapsulation1)=1 μm; (2) E_(electrode)=78 GPa, v_(electrode)=0.44,and h_(electrode)=10 nm; and (3) E_(ILED)=77.5 GPa, v_(ILED)=0.312, andh_(ILED)=2.523 μm. These give the neutral mechanical plane 2.22 μm belowthe top surface. The maximum distance from the ILED is then 1.31 μm fromthe neutral mechanical plane, which gives the maximum strain 0.36% inthe ILED for the experimentally measured wavelength 275 μm and amplitude5.15 μm. The quantum well is 1.011 μm below the top surface of ILED(FIG. 5), and is therefore 0.2 μm to the neutral mechanical plane, whichgives a very small strain 0.053% in the quantum well.

The finite element method has also been used to determine the strains inthe 1.0 μm-thick SU8 encapsulation, 10 nm-thick Au thin film and 2.523μm-thick ILED on 1 mm-thick PDMS substrate. Eight-node, hexahedral brickelements (C3D8) and four-node multi-layer shell elements (S4R) in thefinite element analysis software ABAQUS (2007) are used for thesubstrate and the thin film, respectively. The multi-layer shell isbonded to the substrate by sharing the nodes. Each layer of thin film islinear elastic, while the PDMS substrate is modeled as a hyper-elasticmaterial. The eigenvalues and eigenmodes of the system are firstobtained. The eigenmodes are then used as initial small geometricalimperfections to trigger buckling of the system. The imperfections arealways small enough to ensure that the solution is accurate. As shown inFIG. 4A and FIG. 23, the numerical results give strains that agree verywell with the analytical model.

Simulation of Stretchable ILED of FIGS. 4, B and C: The Island-BridgeDesign

The finite element method has also been used to determine the strains inisland-bridge design of stretchable ILED shown in FIG. 20. Eight-node,hexahedral brick elements (C3D8) in the finite element analysis softwareABAQUS (2007) are used for the substrate, which is modeled as ahyper-elastic material. Four-node, multi-layer shell elements (S4R) areused for the islands and bridges, which are linear elastic. The islandsare bonded to the substrate by sharing the nodes, but the bridges donot. FIG. 24 shows the strain distribution in the top, middle and bottomsurfaces of the ILED as the bridge length is reduced from 310 μm to 250μm. The maximum strain is 0.17%, and that in the quantum well is only0.026%.

Analysis of Flexible/Stretchable ILED System for Strain Sensitivity ofEmission Wavelength

The calculated maximum uniaxial strains in the quantum well of the ILEDsystem are 0.19% tensile in flexible ILED displays, 0.053% tensile instretchable ILED, and 0.026% compressive in stretchable ILED displays.On the basis of the kp perturbation theory (S1, 2) for strain inducedeffect on semiconductor band structures, emission wavelength shift ofthe ILED associated with bending or stretching can be evaluated.

The bending and stretching deformations explored correspond to in-planeuniaxial stress defined as in the x direction here, and the stresses inthe y and z directions are zero (σ_(yy)=σ_(zz)=0) due to freecontraction by Poisson's effect. Thus the strains in these directionsare given by ∈_(yy)=∈_(zz)=−v∈_(xx), where

${\frac{v}{1 - v} = \frac{C_{12}}{C_{11}}},$

and v is Poisson's ratio, C₁₁ and C₁₂ are elastic stiffness constants.For the small stress range examined here, the strain induced bandgapshifts for heavy hole (HH) and light hole (LH) are given byδEg^(LH)=δE_(H)+δE_(S), δEg^(HH)=δE_(H)−δE_(S), whereδE_(H)=a(∈_(xx)+∈_(yy)+∈_(zz)),

${{\delta \; E_{S}} = {\frac{b}{2}\left( {ɛ_{xx} + ɛ_{yy} - {2\; ɛ_{zz}}} \right)}},$

and δE_(H), and δE_(S) are the hydrostatic pressure shift and theuniaxial stress-induced valence-band splitting, respectively (S1-3), anda and b are the corresponding deformation potentials.

For the quantum well (In_(0.56)Ga_(0.44)P) in the ILED structure, theparameters used for the present calculation are a=−7.42 eV, b=1.91 eV,C₁₁11.936×10¹¹ dyne/cm², and C₁₂=5.975×10¹¹ dyne/cm² (S4). Assuming HHis the ground state for the quantum well (S4), the maximum uniaxialmechanical stress induced bandgap shift in the ILED system studied hereis calculated to be ˜7.1 meV (or ˜2.4 nm). This small shift can beconsidered negligible for most applications.

Example 2 Electrically Interconnected Assemblies of Microscale DeviceComponents by Printing and Molding

This example presents approaches for deterministic assembly andelectrical interconnection of micro/nanoscale devices into functionalsystems with useful characteristics. Transfer printing techniquesprovide deterministic control over an assembly process that occurs priorto or simultaneously with a soft lithographic molding step that definesrelief features in a receiving polymer. Filling these features withconducting materials that are processable in the form of liquids orpastes yields integrated interconnects and contacts aligned to thedevices. Studies of the underlying aspects and application torepresentative systems in photovoltaics and solid state lightingindicators provide insights into the process and its practical use.

Unusual microsystems for electronics/optoelectronics, solid statelighting and photovoltaics can be formed with assemblies ofmicro/nanoscale components or material elements to achieve system leveloutcomes that are not possible using conventional approaches. Examplesinclude flexible/stretchable designs, curvilinear layouts and systemsthat exploit heterogeneous materials integration in two or threedimensional layouts. The assembly process can occur either bydeterministic methods based on transfer printing or guided approachesbased on fluidic delivery and surface/shape recognition. In all cases,electrically interconnecting the assembled devices to form integratedsystems represents a practically challenging aspect of the fabrication,particularly for systems in solid state lighting and photovoltaics wherelong interconnect wiring traces with minimal resistances are preferred.The most straightforward and widely explored approaches rely onconventional techniques, such as photolithography, to pattern uniformlayers of metal formed by vacuum deposition (possibly followed byelectroplating). The cost structures, however, preclude their use inmany systems of interest. Conventional soft lithographic methods can beused, but their application over surface topography associated withassembled device components can be difficult. Screen printing or ink jetprinting of pastes or liquid suspensions of conductive particles providealternatives, but their modest resolution limits the utility. Newertechniques that rely on electrohydrodynamic jet printing or directwriting avoid these problems. Achieving adequate throughput with theseserial methods and developing them into forms suitable for realisticapplication are subjects of this example. The research described hereprovides a simple scheme designed specifically to address the classes ofsystems described above; it combines aspects of transfer printing forassembly, with soft imprint lithography and certain aspects of screenprinting for contacts and interconnect. In the following, the basicfeatures of this method are described, and its applications torepresentative systems of interest in monocrystalline siliconphotovoltaics and AlInGaP lighting indicators are demonstrated.

FIG. 24 presents a schematic illustration of the process, in whichtransfer printing for device placement and molding for electricalinterconnect occur simultaneously. The first step involves fabricatingthe devices (i.e. square blocks with rectangular electrode pads; FIG. 24a) on a source substrate using procedures discussed subsequently in thecontext of different demonstration examples. Next, techniques fortransfer printing lift these devices onto an elastomeric stamp/mold withrelief that defines contacts to the electrode regions and trenches forinterconnect. In this example (FIG. 24 b), the relief consists of twodifferent levels such that the devices rest with their electrodes incontact with the highest features; the others are associated withinterconnect. The stamp/mold ‘inked’ with devices then contacts a thinlayer of a liquid prepolymer cast on a target substrate. Allowing thisliquid to flow and conform to the relief, photochemically or thermallycuring it into a solid form and then removing the stamp/mold yields thestructure illustrated in FIG. 24 c. The polymer acts as an adhesive andan encapsulant for the devices, with molded features that define thegeometry of the interconnect wiring. Scraping a conductive paste overthe top surface using methods conceptually similar to those for screenprinting fills the recessed regions in the molded polymer to form theseinterconnects (FIG. 24 d). For the experiments described in thefollowing, a photocurable polyurethane (PU; NOA61, Norland ProductsInc.) and a silver epoxy (H2OE Epo-Tek®, Ted Pella Inc.) served as themold material and the conductive paste, respectively. In certain cases,we found that a thin residue of the PU remained on the contacts of thedevices, necessitating a short reactive ion etching step (50 mtorr, O₂20 sccm, 100 W, 3-5 min; Plasmatherm) to remove this residue just beforeapplication of the conductive paste. The silver epoxy underwent athermal cure at 150° C. for 5 minutes to obtain low electricalresistivity. The casting and curing procedures of soft lithography wereused to form stamps/molds of the elastomer poly(dimethylsiloxane) (PDMS;Sylgard, Dow Corning).

In a first set of experiments, the basic features of this method asapplied to interconnects and contacts to test structures were examined.The molding step relies on established methods for soft imprintlithography. Concepts for using the molded features as trenches to befilled with conductive pastes, and accomplishing the molding at the sametime as printing are both unusual aspects of the process reported here.The filling procedures involve first dispensing a line of silver epoxyalong one edge of a flat region of the substrate, located a short (e.g.3-5 mm) distance away from the molded features. As an implement forscraping this epoxy over the surface, we used a slab of PDMS roughly 3cm long, 1 cm thick and with a width somewhat larger than that of themolded substrate. This element has a ˜45° beveled edge, similar tosqueegees used for screen printing. Scraping this edge across thesubstrate at an angle of ˜30 degrees several times filled the trencheswith epoxy and left only small amounts of residue on the top surfaces.Scraping several additional times with another PDMS element soaked inacetone removed these residues. FIG. 25 a shows a pattern of conductingfeatures formed in this fashion on a molded layer of PU (20 μm depth) ona substrate of polyethylene terephthalate (PET). These resultsillustrate the range of feature sizes (line widths 20-200 μm, lengths0.2-2.0 mm, in straight, curved and zig-zag geometries, and in text) andshapes that can be formed easily, and the good levels of uniformity thatare possible. The limit of resolution is determined by the sizes ofparticles in the silver epoxy (10-15 μm), rather than by the fidelity inthe molding step. FIG. 25 b shows cross sectional views of lines formedwith aspect ratios (depth to width) of 1 and 0.1. The limits at the highand low ends of this range are defined, respectively, by inability topush epoxy into deep, narrow features, and tendency to scrape itcompletely away from the center regions of shallow, wide features.Decreasing the viscosity and particle sizes in the epoxy can improve theformer aspect; increasing the stiffness of the slab of material (PDMS inthis case) used to scrape the epoxy into the grooves can improve thelatter. Independent of dimension in the acceptable range, we foundvalues of electrical resistivity (3.0-6.0×10⁻⁴ Ω·cm) roughly two ordersof magnitude higher than bulk silver (1.6×10⁻⁶ Ω·cm), for curingtemperatures of 150 and times of 5 minutes, consistent withspecifications from the vendor. Contacts to devices and electricalcrossovers can be formed in the manner of FIG. 24. FIG. 25 c shows suchan example, where metal pads (Cr/Au, 100/1000 nm; 500×500 μm) formed ina square array (1.5 mm pitch) on a PET substrate provide an equivalentof the devices in FIG. 24. Defining trenches in PU using a stamp/moldwith a design similar to that of FIG. 24 followed by filling with silverepoxy yielded the structure shown in the image of FIG. 25( c). Thebottom left and right frames provide a schematic cartoon illustrationand a top view optical micrograph, respectively. The lines here havewidths of 100 μm and depths of 20 μm. The contacts to the electrode padsare defined by molded features with depths of 40 μm and lateraldimensions of 100×300 μm. Current/voltage data (FIG. 25( d)) collectedby probing contact pads to different combinations of row (r1, r2, etc)and column (c1, c2, etc) electrodes verifies electrical continuity alonggiven columns and rows and electrical isolation (i.e. >GΩ) between allother pairs of lines.

To demonstrate this concept in real devices, AlInGaP light emittingdiodes (LEDs; 250×250 μm) formed in ultrathin (2.5 μm thick) layoutswere used. Here, the printing step to transfer these devices from a GaAswafer to a glass substrate occurred first, followed by molding to definecontacts and interconnect. FIG. 26( a) shows a set of six such LEDs,with an independent pair of electrical leads to each. The top insetprovides a top view optical micrograph. The three devices in the middlewere connected to a power supply to induce light emission, for thepurpose of illustration. The current/voltage characteristics shown inFIG. 26 b are similar to those observed in devices (non-ohmic contacts)interconnected with conventional procedures of photolithography andliftoff.

Microscale monocrystalline silicon solar cells provide another deviceexample. Here, collection of five such cells were formed intointerconnected arrays for a mini-module using the schemes as shown inFIG. 24, where printing and molding occurred simultaneously. See FIG. 27a. The process steps for fabricating the cells appear elsewhere. Eachcell consists of a bar of monocrystalline silicon (width, length andthickness of 50 μm, 1.55 mm and 20 μm, respectively) with ohmic contactsof metal (Cr/Au, 100/1000 nm; 50 μm width and 100 μm length for the pcontact; 50 μm width and 1.4 mm length for the n contact). FIG. 27( b)shows a sample, with an inset that provides a cross sectional view ofpart of the structure. In these systems, illumination occurs through thebackside surface of the transparent substrate; the interconnect linesand metal layers serve as reflectors. FIG. 27( c) gives current/voltagecharacteristics carried out at room temperature using a DC source meter(Model 2400, Keithley) operated by Labview5®, and a 1000 W full spectrumsolar simulator (Model 91192, 4×4 inch source diameter, ±4° collimation,Oriel) equipped with AM 0 and AM 1.5 direct filter. The efficiency(E_(ff)) and fill factor (FF) of this solar cell, corresponding tomeasurement on all five interconnected cells in the module, were 6.5%and 0.61 respectively, obtained using standard procedures andconsidering only the geometrical sizes of the cells (not explicitlyseparating flux from the sidewalls). These properties are in the samerange as those of arrays of similar devices interconnected usingconventional procedures.

In summary, the procedures reported here might provide an attractivesolution to electrical interconnection of classes of systems thatincorporate assemblies of micro/nanoscale devices or material elements.Although their use in prototype devices for photovoltaics and lightingindicators demonstrates the key aspects, the same methods can also beused to establish electrodes and/or interconnects in related systemsthat use micro/nanoscale material elements, such as nanowires,nanomembranes, nanotubes, and others. The printing and molding can occureither sequentially or simultaneously, depending on requirements. Thefinal, embedded configurations of the devices that result from thisprocess have practical advantages for encapsulation. The ultimate limitsin the resolution are defined by the soft imprint molding procedures(e.g. ˜1-2 nm for PDMS molds) and the conductive pastes (e.g. 5-100 nmfor Au or Ag nanoparticles). Their use in realistic applications willalso be limited by achievable registration of the stamp/mold elements tothe device components or material elements. Flexible sheets of plasticor glass can form support structures for thin layers of PDMS, to reducedistortions to one or two micron levels over areas of hundreds of squarecentimeters, or larger. The characteristics of the methods describedhere, their simplicity and potential for low cost operation over largeareas, and the diversity of materials and devices with which they can beapplied suggest a potential for broad utility.

Example 3 Printed GaAs LEDs

GaAs LED device fabrication starts out with the epitaxially grown LEDwafer. Epitaxial layers of GaAs wafers are shown in FIG. 28. The stackstructures of this particular GaAs LED wafer used for the experimentsare also listed in Table 1 below.

From the multi-quantum well (MQW) which is shown as layer 5 in FIG. 28and Table 1, barrier, cladding, spreading, and contact layerssymmetrically distributed to form a Vertical-type LED (VLED). Epitaxialstructures for GaAs LED are, however, not restricted to this particularstructures. There are many variant structure designs for differentpurposes and applications, and transfer-printing technology should becompatible regardless of this epitaxial structure designs.

The processing schematics for μ-GaAs LED is shown in FIG. 29. Thefabrication process starts out with the commercially available GaAs LEDepitaxial wafer with an embedded sacrificial layer as shown in FIG. 28.First, SiO₂ layer is deposited onto the GaAs LED wafer andphotolithographically patterned SiO₂ layer serves as an etch mask forthe isolation step which is carried out by dry-etching (i.e. ICP RIEwith Cl₂). GaAs can also be isolated using wet etchant (i.e. HCl), andPhoto-resist (PR) can be sufficient as an etch mask in this case. Thepoint is that SiO₂ can be any other etch mask depending which isolationroute is considered. Once GaAs LED cells are isolated on the host wafer,heterogeneous anchors are photolithographically defined as illustratedin FIG. 29. Scanning Electron Microscopy (SEM) images along with OpticalMicroscopy (OM) images of these GaAs LEDs after isolation (A), anchoring(B), and printing (C) processes are shown in FIG. 30.

TABLE 1 Epitaxial Layers of GaAs LED wafer Layer Thickness ConcentrationLayer Name Material (nm) Type Dopant (cm⁻³) 1 Contact GaAs 5 P C1.00E+19 2 Spreader Al_(0.45)Ga_(0.55)As 800 P C 1.00E+18 3 CladIn_(0.5)Al_(0.5)P 200 P Zn 3E17 to 6E17 4 BarrierAl_(0.25)Ga_(0.25)In_(0.5)P 6 —  —  <1E16 5 Well In_(0.55)Ga_(0.44)P 6 ——  <1E16 6 Barrier Al_(0.25)Ga_(0.25)In_(0.5)P 6 —  —  <1E16 7 CladIn_(0.5)Al_(0.5)P 200 N Si 1.00E+18 8 Spreader Al_(0.45)Ga_(0.55)As 800N Si 1.00E+18 9 Contact GaAs 500 N Si 4.00E+18 10 Al_(0.85)Ga_(0.04)As1500 N Si 1.00E+17 11 GaAs 1500 N Si 1.00E+17 12 Al_(0.85)Ga_(0.04)As500 N Si 1.00E+17 13 Substrate GaAs N Si  >1E18

Example 4 Printed GaN LEDs from Silicon

GaN device fabrication begins with a host wafer with a suitableepitaxial layer stack as shown in FIG. 32. This particular GaN LEDstructures are epitaxially grown on Si (111) wafer. However, similarfabrication process can be employed on GaN LED structures grown onSapphire or any other host substrates.

Following from FIG. 33, access to the n-GaN is achieved by a) ICP-RIEetching of the p-GaN and quantum well region. Mixed metal ohmiccontacts, first n-contacts then p-contacts, are subsequently depositedand annealed with a standard high temperature rapid thermal annealingprocess. Device isolation is achieved via patterning Si₃N₄ and a thickmetal etch mask and ICP-RIE etching for the isolation. Since this systemis concerned with utilizing the anisotropic etching characteristics ofthe underlying Si(111) substrate, sufficient etch depth into the Sisubstrate must be obtained. Potassium hydroxide (KOH) orTetramethylammonium hydroxide (TMAH) is used as the anisotropic etchantof Si(111) which results in suspended devices tethered to the host wafervia anchor bars as shown in FIG. 34. It is, however, not restricted toused KOH or TMAH. As a matter of fact, drying etching silicon usinggases such as SF₆, CF₆, and XeF₂, could isotropically etch underlyingsilicon to generate free-standing μ-LEDs chiplets. For KOH-based etchingsystem, Si₃N₄ is used in the previous etch mask to serve as a protectivebarrier to ohmic contacts from the harsh conditions of the stronglyalkaline KOH solution. Individual devices are removed from the hostsubstrate via contacting with a soft elastomeric stamp, namely PDMS, andpulling the stamp quickly in the vertical direction. This device is thentransferred to a secondary substrate coated with a thin polymer adhesivelayer (i.e. PDMS, SU-8, polyimide, BCB, sol-gel silica, etc) or withoutany such layer.

Utilizing a step-and-repeat process, devices can be removed from a verydense array and be printed to a sparse array of any desired spacing. Anoptical image of a donor substrate during the step-and-repeat process isshown in FIG. 35. It shows retrieved LED cells which are transferredonto the foreign substrate. This step-and-repeat concept is notrestricted to GaN LED, but can be employed in wide variety of materialsincluding GaAs LED, which is shown in FIG. 36. The transfer can beaccomplished with a patterned or an un-patterned stamp. The transfer canbe facilitated by the use of specialized relief structures, embeddedactuators (balloons, local heaters, and the like) or by externallyapplied forces or radiation (laser exposure, etc). In some cases, it ispossible, for example, to print the LEDs directly onto a pre-metalizedsubstrate to achieve transfer and, at the same time, electricalinterconnect and interface with heat spreading structures. In additionto these variants in printing, the processing sequence of FIG. 33 can beimplemented in different orders—e.g. the ohmic contacts can be definedon the foreign substrate, after printing.

Current-voltage (I-V) characteristics of undercut and printed deviceswere measured using an Agilent 4155C Semiconductor Parameter Analyzer asshown in FIG. 37( b). Light emission spectrum was collected using aspectrometer from Ocean Optics and according to FIG. 37( c) the peakemission wavelength is 472.3 nm. As shown in FIG. 37( b), an individualμ-GaN LED exhibits forward bias voltage of ˜4.2V at the forward currentof 50 mA with an emission wavelength at around 470 nm.

Experimental results have shown slight etching of the GaN stack uponextended exposure (˜20 min) to KOH. FIG. 38 shows two SEM images of a100 μm×100 μm device immediately following the ICP-RIE deep etching withthe Ni/Si₃N₄ etch mask still intact. Slight sidewall striations can benoticed due to the anisotropic etching of the ICP-RIE. Following KOHundercut of the device, moderate roughening of the device sidewall isobserved.

Etching of GaN is very slow and is considered negligible in the contextof LED fabrication, i.e. sidewall roughening has no effect on deviceperformance. If pristine sidewalls are desired, an additionalpassivation step can be included in the fabrication process, FIG. 39.Following ICP-RIE deep etching, a) Ni etch mask is removed followed bySi₃N₄ deposition by PECVD. A b) timed RIE etch then removes Si₃N₄ fromthe trench “floors” and c) SF₆ RIE treatment will etch the underlying Sisubstrate. The device e) can then be undercut in KOH then f) transferprinted to a secondary substrate followed by buffered oxide etchantremoval of the remaining Si₃N₄.

Printed GaN LEDs from Sapphire

Due to the relatively large mismatch in lattice constants of GaN andSi(111), sapphire has always been the predominant substrate for GaNgrowth. Sapphire, however, is very inert, making etching of the materialvery difficult. Grinding, polishing and other process approaches mightbe suitable. An alternative route to printed devices from a sapphiresubstrate (also applicable to SiC and other substrates) utilizes thelaser lift-off method, which is shown in FIG. 40. Alternatively,releasing the GaN stack from handle wafer by selective etching of asacrificial layer are also shown in FIGS. 41 and 42.

Laser Lift Off with Wafer-LED Layer Bonding

FIG. 40 shows steps for processing GaN LEDs grown on a sapphiresubstrate then wafer-bonded to a Si (111) substrate and removed from thesapphire via laser lift-off. The first steps include b) n-contactdeposition and annealing then c) wafer bonding and laser lift-off.Exposed interface between GaN and sapphire is easily delaminated andtransferred from sapphire to receiver wafer, as can be shown in c),d).Freestanding GaN layers are fabricated for LED devices by siliconundercut etching with KOH (similar to procedures described in theprevious sections), GaN buffer layer elimination (via polishing, asillustrated here, or by etching or related procedures) and e) n-contactelectrode patterning. The inset image shows experimental results ofsections of GaN epimaterial bonded to a Si (111) wafer coated with Au.GaN structures here are composed of 5×5 mm² squares on 2 inch sapphire.Receptor wafer is 3 inch diameter with <111> direction. Trench etchingand other approaches, not explicitly indicated here, are often necessaryto achieve high yields in this overall process flow.

Sacrificial Layer for Undercut Etching: PEC Etching

As mentioned above, sacrificial layer inserted in GaN stack can be usedas an alternative to wafer bonding. Various sacrificial layers (InGaN,SiO₂, AlAs, Si₃N₄, ZnO, and etc.) can be used which are etchedselectively in solutions (i.e. HF, HCl, and H₃PO₄). Etching methods arevarious. Directional wet etching, PEC (photoelectrochemical) etching andEC (electrochemical) etching can be utilized to form freestanding GaNLED layers suitably configured for printing. FIG. 41 presents oneexample.

FIG. 41 presents InGaN sacrificial layer and selectively etching of thislayer by the PEC etching method. Here, a sacrificial layer such as InGaNlayer is inserted between GaN stack and GaN buffer layer. Selectiveetchants (such as HCl, KOH, and etc) can be utilized for PEC etching(i.e. GaN etching rate ˜0). After dry etched a), entire devicesubstrates on sapphire are etched with PEC etching. The metal in thefield serves as a cathode during PEC etching b) in diluted HCl (0.004M)with 1000 W Xe lamp. The lamp photo-generates carriers and associatedPEC etching, while an intentionally doped GaN film filters out the lightwith energy higher than band gap of GaN, thereby limiting etching to thelower band gap InGaN sacrificial layer. Selectively undercut GaN devicesare transferred by protruding PDMS mold, d).

Sacrificial Layer for Undercut Etching with EC (Electrochemical Etching)

FIG. 42 explains one of examples of an EC etching method. It is quitesimilar with PEC etching, however, photo irradiation is not needed inthis system. The electrolyte can help a sacrificial layer be decomposedand etched. In panel (a) of FIG. 42, GaN/InGaN multilayer structures arecovered with a passivation layer, such as SiN_(x) or SiO₂, and a cathode(e.g., Ti/Au) is fabricated on the InGaN sacrificial layer. Panel (b) ofFIG. 42 shows connection of the cathode to power supply in anelectrolyte (e.g., 0.008 M HCl). As shown in panel (c) of FIG. 42, thesacrificial layer can be removed, followed by removal of the passivationlayer, for example with buffered oxide etchant (BOE). Finally, as shownin panel (d) of FIG. 42, the structures are selectively transferred bytransfer/contact printing

Sacrificial Layer for Undercut Etching: Selectively Wet Etching

Sacrificial layers that can be removed without PEC or related schemesfor selectively are also possible.

FIG. 43 presents an example of wet etching strategy for freestanding GaNLED cells. ZnO buffer layer can be used for template of GaN epitaxialprocess. ZnO layer is selectively etched by 5% diluted NH₄Cl in water.Materials such as SiO₂ can be used for passivation, as they are notremoved by this etchant.

Example 5 Anchoring Structures

During the process of generating free-standing μ-LEDs structures (i.e.μ-GaAs LED, μ-GaN LED, and etc), anchoring structures were used to holdμ-LED chiplets in place preventing them from being disturbed or beingdisplaced. Various anchoring schemes are proposed in this example. Inlarge, the anchoring structures can be divided into two differentcategories: Heterogeneous anchoring and Homogeneous anchoring.

Heterogeneous Anchoring Structures

Heterogeneous anchoring represents anchor structures that are differentmaterials than the chiplet materials. (i.e. polymer anchor, and etc).One type of heterogeneous anchoring system is shown in FIG. 44.

In this particular heterogeneous anchoring structure shown in FIG. 44,photolithographically defined photoresist (PR) is used as an anchor. Itis, however, not restricted to photoresist. In fact, any material (i.e.organic, inorganic, ceramic, and etc) that withstands the etchant oretching species can be served as an anchor. As illustrated in the FIG.45, various geometries of heterogeneous anchoring structures can beemployed depending on process conditions. Anchoring geometries shown inFIG. 45 are only few examples from many possible variances.

Homogeneous Anchoring Structures

In the case of μ-GaN LED chiplets on silicon (111), natural homogeneousanchors are formed if chiplets are aligned parallel to the [110]direction of the silicon (111) wafer. Anisotropic Si etchant (i.e. KOH,TMAH, and etc) exhibits significant etch rate variation depending oncrystalline direction they are etching. For example, KOH etches [110]and [100] direction several hundred times faster than [111] direction.In other words, if μ-GaN LED chiplets are aligned parallel to [110]direction, etch rate difference between (110) and (111) planes producesa natural anchoring system as shown in FIG. 46. Since these anchors aresame material as the μ-GaN LED chiplets, we refer them as Homogeneousanchors.

Example 6 Encapsulation & Interconnection

Once μ-LED cells are transfer printed onto a foreign substrate, thecells can be passivated and encapsulated in a manner that leaves thecontact regions exposed for electrical interconnection. On conventionalLED process, electrical connection from LED to the external pins areoften realized via wire bonding. Wire bonding process requires the ballsize of about 100 μm in diameter as shown in FIG. 47.

Consequently, the light-emitting area effectively gets reduced by thesize of the ball required for the wire bonding process. Unless the ballsize for the wire bonding is dramatically reduced, reducing the LED diesize simply becomes unrealizable. Recent work with GaAs based devicesdemonstrates the ability to use planar processing techniques toestablish interconnects that are much smaller than those possible withwire bonding. These strategies can also be implemented with GaN devices,alone or in combination with wire bonding, screen printing, transferprinting/molding and other approaches.

Encapsulation Via Back-Side Exposure (EBSE)

This example describes a self-aligned process that is referred to hereinas Encapsulation via Back-Side Exposure, as illustrated in FIG. 48.

First, photosensitive polymers (negative tone) can be spin-coated orspray-deposited onto the transferred μ-GaN LEDs on a transparentsubstrate. Photosensitive polymers with a sufficient thickness canencapsulate the entire substrate conformally as illustrated in FIG. 48.P-ohmic contact metal composition can be selected to have a hightransparency in the emission wavelength and but only partialtransparency at the UV wavelengths for the process of FIG. 48. Thickcontact pads are deposited on P-ohmic contact metal. By taking advantageof transparent nature of the substrate and reflective nature of theP-contact pads, the photosensitive polymer layer can be exposed from thebackside of the substrate with the optimum exposure dose. During theback-side (flood) exposure step, thick contact pads on the LED chipletsimply serve as self-aligned masking layers such that the photosensitivepolymer in these regions is not exposed by the backside irradiation.These regions can be selectively removed during a subsequent developingstep. After the final curing step, conventional photolithography orrelated approaches can be used for the interconnection between LEDs.Many variations of these basic concepts are possible.

Scanning Electron Microscopy (SEM) and Optical Microscopy (OM) images ofμ-GaN LED after Encapsulation via Back-Side Exposure process are shownin FIG. 49 above. Profilometer data on μ-GaN LED after the processappears in FIG. 50 below. Blue and Black profiles represent theas-printed μ-GaN LED cell before the encapsulation process and printedμ-GaN LED cell after the encapsulation process, respectively.

A fully interconnected string of μ-GaN LEDs are shown in FIG. 51 above.Incorporating a series connection between μ-GaN LEDs results in highlyuniform light output from one μ-GaN LED to another because of identicalcurrent flowing through these μ-GaN LEDs. Furthermore, two strings offive μ-GaN LEDs connected in series are shown in FIG. 52 below.

Example 7 Molded Interconnection for μ-LEDs

As an alternative to the process of FIG. 48, LED isolation andinterconnection can be done in a single step (or multiple, sequentialsteps) using the molded interconnection method as illustrated in theFIG. 53 and FIG. 54.

As illustrated in FIG. 53 above, selectively transferred LEDs can serveas a template for creating a master for the PDMS mold. Byphotolithographically patterning photosensitive polymer (i.e. Su-8 fromMicrochem), trenched patterns can be fabricated leading from the LEDcontacts. These trenched patterns can be designed following the desiredinterconnection patterns. Therefore, the molded elastomer stamp usingthis master would have protruded interconnection structures. 3Dpatterned elastomer stamp can be used to selectively pick up LEDs fromtheir donor substrate, and transfer them onto the target substrate usingphoto-curable polymer such as NOA (Norland Optical Adhesive) creatingembossed structures. Elastomer stamp can be simply peeled off afterphoto-curing adhesive polymer resulting in trenched patterns for theinterconnection between LEDs similar to the master substrate. Whenapplied silver paste would simply fill up the previously createdtrenches and silver paste on the top surface can simply be scrapped offleaving silver paste only in the trenched regions. Resulted silver pastein the trenched regions can now serve as an interconnection between LEDsand external contacts as illustrated in FIG. 54.

An optical image and the electrical measurement on metalized LEDs areillustrated in FIG. 55.

Furthermore, this molded interconnection approach can be slightlymodified to generate by including the opaque or reflective layers on theareas of stamp that contact the device electrodes as illustrated in FIG.56. In this way, the photo-curable molding material would not beexposure to irradiation and hence be left uncured only on thoselocations enabling easy removal with appropriate solvent. In FIG. 56(a), metal is deposited or transferred only on the surface of PDMS relieffeatures which is supposed to be in contact with electrodes of devices.Another approach is depicted in FIG. 56( b) where patterned mask whichcorresponds to electrodes of device is place on the backside of PDMSstamp during the UV curing effectively serving as a masking layer.

The ultimate limits in the resolution of the molded interconnectionapproach are defined by the soft imprint molding procedures and the Agparticle size. Average Ag particle size used in the experiment above isabout 10˜15 μm, which makes it difficult to generate finerinterconnection. Using Ag nano-particles with the average size of 5 nm˜100 nm, the resolution of molded interconnection could improvedramatically down to sub-micron regime.

Besides the molded interconnection approach, e-jet printing approach anddirect-ink writing approaches can also be used as alternativeinterconnection schemes.

Example 8 Mesh Interconnection for Vertical LED (V-LED)

Interconnection for a vertical LED (a type of LED where electricalcontact for N and P are made top and bottom as shown in FIG. 58) can beaccomplished by Mesh Interconnection approach, which is illustrated inFIG. 59.

Fabrication Process for the Mesh Interconnection is illustrated in FIG.59. As shown in FIG. 59, metal mesh gets transfer printed onto theplastic substrate with the adhesive layer. Since metal-mesh structure isonly partially covering the adhesive layer underneath, μ-LEDs caneffectively be transfer-printed onto the substrate. These metal mesh cannot only serve as a electrical connection to the printed μ-LEDs, butalso as a heat sink. A thin adhesive layer of PDMS (although it is notrestricted to PDMS) facilitates printing onto the glass substrate. Aphoto-patterned layer of epoxy on top of the devices prevents shortingof the top film to the bottom mesh.

Serial Interconnection Vs. Parallel Interconnection for μ-LEDs

μ-LED, like any diode, has an exponential relationship between currentand voltage. In other words, a slight variation in the forward voltagebetween cells could result in a much larger difference in the operatingcurrent, and hence different luminescence. When a large number of μ-LEDsare connected in parallel, a μ-LED with a smaller forward voltage, orturn-on voltage, would draw most of the supplied current instead of allμ-LEDs receiving the same amount of current. In a series connection,however, all μ-LEDs would receive equal amount of current since there'sonly one possible current path in a serially connected string of μ-LEDsas illustrated in FIG. 60. As shown in FIGS. 60 and 61, combination ofseries/parallel connection generates more uniform light output fromlarge number of interconnected μ-LEDs.

Planar Interconnection

As mentioned in previous section, the ultrathin property of theseprinted μ-LEDs enable a conventional planar interconnection schemes asillustrated in FIG. 62. Conventional LEDs with vertical thickness in anorder of several hundred μm, simple planar interconnection schemesuggested here becomes extremely challenging or almost impossible toachieve due to the extremely high step coverage, which is why thewire-bonding approach has become the main stream approach as shown inFIG. 47 earlier.

Example 9 Stretchable Lighting System Based on Printed μ-LEDs

The interconnects of the spatially independent micro-lens array can befabricated in a serpentine-like (not shown) or accordion-like (shown inFIG. 63) fashions to serve as a force dampening mechanism. With such adesign, the module can be stretched and bent but the interconnect willstretch and flex so as to absorb the lateral forces exerted due thechange in relative position of each pixel keeping the curvature of themicro-lens unchanged. Furthermore the surface of these micro-lens can beroughened to serve as the diffusion stage.

The approach in FIG. 63 is used for creating a stretchableinterconnection, while that of FIG. 64 is used for creating stretchableμ-LED, per se, for possible outcoupling of the light output viastrain-induced modification of the band structures of p-LEDs.

Example 10 Enhancement in Light Extraction from μ-GaN LEDs

Recent research on GaN blue LEDs has led to a rapid development of thequality of the devices, pushing the performance to ever higher levels.GaN based LEDs are expected to soon take over conventional(incandescent, fluorescent, and compact fluorescent) lighting systemsbut progress has been slowed by the relatively poor light extraction.Due to the high refractive index (˜2.5) of GaN, the critical angle forlight escape into air is ˜23.6°, as calculated by Snell's law. Lightincident upon the inside surface outside of this angle is reflected backinto the device where absorption in the epi-layers subsequently quenchthe light. To this end, several technologies can be applied to thisflexible array of GaN LEDs which will enhance the optical performance ofthe system.

Example 11 Textured and/or Roughened Surface for Improved LightExtraction

The normal, “mirror-like” surface of a GaN LED leads to a large fractionof light to be internally reflected thereby decreasing the lightextraction efficiency of the device. A method to increasing lightextraction is to roughen to the bottom surface serving as a means toreducing internal reflection and scattering the light outwards from theLED as shown in FIG. 65.

Fabrication of a roughened surface will closely follow established μ-GaNLED fabrication methods, as described previously. Following completedevice fabrication individual pixels will be undercut by anisotropicpotassium hydroxide (KOH) etching of the silicon substrate, performed inan environment free of ultra-violet (UV) light (i.e. cleanroom). Uponcomplete undercut, a plasma enhanced chemical vapor deposition (PECVD)passivation layer of Si₃N₄ is deposited to protect ohmic contacts andsidewalls of the fabricated device. Further etching in KOH in thepresence of UV light will promote the photoelectrochemical (PEC) etchingof the exposed (bottom) side of the μ-GaN LED, forming pyramidal shapedstructures that serve as efficient light scattering centers as shown inFIG. 66.

These LEDs are well suited for bottom emission, with the potential toenhance light extraction by 100% or more. Bottom emission can beefficiently achieved by using a thick, reflective μ-contact. Contactschemes utilizing Pt/Ag as the μ-contacts have reportedly shownreflectance values of 80%. Additional reflectance can be realized by theaddition of a top-side reflector made of thick Al or Ag whichdemonstrate very high reflectivity at 470 nm.

Schematics for optically enhancement with outcoupling is shown in FIG.67 below. Although schematics in FIG. 67 is illustrated with μ-GaN LEDfrom Sapphire substrate using Laser Lift-off approach, the concept ofusing GaN cones structures for outcoupling the light is not restrictedto this particular process. After the wafer bonding ((a)˜(d)), residualGaN buffer layer could be selectively etched by crystallographic wetetching, (e). GaN buffer layer can be etched by H₃PO₄ etchant and PECetching. Inset SEM image shows an example of GaN cones made by thecrystallographic wet etching (D. A. Stocker et al Appl. Phys. Lett. 73,2654 (1998)). Below two illustrations demonstrate the light emissionpath comparison between LEDs with GaN cones and without GaN cones. BySnell's law, impinged light by the interface is randomly emitted. On theother hands, with GaN cones device light can be emitted with straightpropagation after impinged on surface.

Micro-Lens, Polymeric Molded Structures for Improved Light Extraction

Towards the realization of highly efficient top emitting LEDs,micro-lens arrays can be incorporated into the final device. Lensstructures, being fabricated from a higher index material (typically apolymer of n˜1.5) increase the light extraction cone at the GaN/polymerinterface. The lens shape is better capable of extracting light from thepolymer medium to surrounding air.

Micro-lens arrays can be fabricated through a series of establishedphotolithographic techniques. Processing begins with patterning of aphotoresist. Elevated temperatures will cause the photoresist to reflowin a manner that reduces surface energy, resulting in a lens-like shape.This pattern can be captured by molding an uncured polymer such as PDMSto the micro-lens array. Final lens geometry is obtained by molding anoptically clear polymer (i.e. Norland Optical Adhesive) to the PDMSmold. The lens can be removed from the mold, aligned, and laminated tothe LED array.

The above micro-lens geometry can be optimized to an LED array when thearray is left in an un-bent state. Upon bending, lateral forces in thelens array will cause deformation in the individual lens structuresthereby decreasing the optical performance of the lens. In an effort toachieve total flexibility the following system is proposed that offers aspatially independent lens array in which the movement of a pixel doesnot exert lateral forces conducive to lens deformation on its neighborpixel.

Processing of a spatially independent lens array follows a similarfabrication route as above. Pixel interconnects are patterned along witheach micro-lens feature. The independent nature of this array arises inmolding the polymer encapsulant (step “e” in FIG. 70) when asufficiently thin polymer film is spun such that only the depressed(lens and interconnect) features are filled. Upon removal from the moldthe spatially independent lens array is then aligned and laminated tothe micro-LED array.

Processing schematics for fabricating polymeric patterns for opticalenhancement of μ-GaN LED is shown in FIG. 71. After wafer bonding((a)-(d)) and residual GaN polishing, polymeric patterns can be formedby molding, imprint, colloidal lithography, etc. Patterned polymericstructures can manipulate light intensity, light wave length shift. Dutyratio and polymeric beads size can control emission properties.

Fabrication of micro-lens and polymeric structures are not restrictedonly to the above processes. Micro-lens can also be fabricated invarious approaches such as casting, molding, imprint, colloidallithography, screen printing, ink-jet printing, E-jet printing, and etc.These micro-lens and polymeric structures can be either fabricated onthe already-printed μ-GaN LED, or can be fabricated on the differentsubstrate and be transfer-printed onto the μ-GaN LED afterwards.

Furthermore, besides those added modifications (i.e. micro-lens, conestructures, and etc), the thin and small geometries of these printedμ-LED results in higher extraction efficiency per unit area. Theseprinted μ-LED have a size much smaller (100 μm² to 10,000 μm²) thanconventionally LEDs (100,000 μm² to 1,000,000 μm²). In other words,μ-LEDs fabricated here are as much as 10,000 times smaller thanconventional LEDs. Attributing to its micro-size effects as well as tomore efficient usage of the injected current, light from the quantumwell is more likely to be escaped from the LED because of smaller numberof internal reflections and larger surface-to-volume ratio.

Example 12 Merging the Light Output from the Bi-Direction LED

μ-LED printed onto a transparent substrate such as a glass or a plasticexhibits bi-axial illumination as shown in FIG. 72. In other words,light from the printed μ-LED can be emitted from the top as well as fromthe bottom.

Highly reflective metals (e.g. Al, Ag, Pt, and etc) can be deposited onthe top of the printed μ-LED or μ-LED can printed on highly reflectivemetal foil to reflect the light to merge the light emission intoone-direction, which in turn increases the light output.

As illustrated in FIG. 73, a micro-lens can be fabricated or placed onthe printed μ-LED. These micro-lenses can simply be molded usingphoto-curable resin as illustrated in the figure above or be fabricatedelsewhere and be transfer-printed onto μ-LED. Highly reflective andthermally conductive metals, such as Ag, can be plated, evaporated, orsputtered on top of the these structures to create a mirror-likestructures to reflect the light emitted from the printed μ-LED. Thesereflectors can also be placed on the side to direct the light emittingfrom the edges of printed μ-LED. As mentioned in this example, the abovesystem is suited for the margining the bi-directional light output intothe bottom emission. However, a similar system can be incorporated intotop emission system simply by transfer-printing μ-LED onto the alreadyfabricated the micro-lens system with a reflective mirror. Additionally,re-directed light output using various approaches mentioned above,optical fibers can be incorporated in various ways to manipulate thefocused light direction arbitrary. Furthermore, these reflectors canalso be served as a heat sink due to its high thermal conductivity.

Example 13 Multiple Stacks of μ-LEDs

Epitaxial wafer of compound material is a considerably more expensiveprocess than the Cz process of silicon. Cost saving process forgenerating epitaxial wafer is proposed in FIG. 74. As shown in FIG. 74,multiple μ-LED layers can be grown initially. Although the schematic inFIG. 74 illustrates the multi-layer GaAs LED structures, the similarconcept can be employed in GaN-based LED or any other structures fromIII-V and III-N compound materials. After the lattice mismatch issuebetween the substrate and the epitaxial layers is resolved by the growthof a buffer layer, an appropriate sacrificial layer and active LED layercan be grown in alternating fashion as illustrated in the figure. Thisgrowth process can be repeated several times to generate multiple layersof identical sacrificial layer and the active layers. μ-LEDs from thetop most layer (or the 1st layer of μ-LEDs as depicted in the figure)can be defined in the free-standing fashion by undercutting thesacrificial layer as shown in the figure. These μ-LEDs can be transferprinted in various ways as we have mentioned in previous sections. Oncethe 1st layer is fully processed and transfer printed onto the foreignsubstrate, the 2nd layer is exposed and is ready to be processedidentically as the 1st layer was processed. Hence, we can generate muchmore μ-LEDs from the single wafer. Hence, the total cost of fabricatingμ-LEDs can get effectively reduced.

Example 14 Thermal Management for μ-LEDs

When a plastic substrate is used, thermal management of μ-LEDs isimportant because a plastic substrate is intrinsically an insulator.Printed μ-LED, however, has a size much smaller (100 μm² to 10,000 μm²)than conventionally LEDs (100,000 μm² to 1,000,000 μm²). In other words,μ-LEDs fabricated here are as much as 10,000 times smaller thanconventional LEDs. Sparse array of smaller μ-LEDs could exhibit betterthermal distribution than one larger LED because generated heat for asmaller μ-LED is far less than a larger conventional LED. Furthermore,sparser array geometry enables better heat dissipation than a largerconventional LED simply because heat generated for a larger conventionalLED is more concentrated around the LED itself.

FIG. 75 illustrates the thermographic images of printed μ-LED on aplastic substrate without any heat sink in the proximity. The baselinetemperature is fixed at 70° C. for this particular experiment.

Metallic Heat Sink on Top of μ-LEDs

Placing a thermally conductive heat sink in a proximity of the printedμ-LED can significantly improve the thermal dissipation from the printedμ-LEDs. A cross-sectional schematic of such a system is illustrated inthe FIG. 76.

An electrical insulating dielectric layer with a higher thermalconductivity than organic polymer (i.e. SiN with thermal conductivity of30 W/mK compared to 0.24 W/mK of PET), can be deposited on top of theprinted μ-LEDs on a plastic substrate. A material with a high thermalconductivity, such as Ag and Cu, can be deposited on top of the μ-LEDwith an dielectric layer (i.e. SiN) in between for electrical isolation.Furthermore, a dielectric layer such as SiN can be controlled such thata very thin layer of a SiN layer is enough for electrical isolation.

Transfer Printing Materials with High Thermal Conductivity on Top ofμ-LEDs

The materials for the heat sink can be metals, or any other materialwith a high thermal conductivity, such as a polycrystalline diamondshown in FIG. 77. These materials can be transfer-printed via eitheractive or passive system.

Use of printed μ-Diamond as a heat sink is shown in FIG. 77. μ-Diamondcan be easily formulated in Chemical Vapor Deposition (CVD) process at alow cost. Grown μ-Diamond layer can be patterned and be lifted off fromthe mother wafer similar to μ-LED process described previously. Theseμ-Diamonds can be transfer printed on top of already-printed μ-LEDserving as a efficient heat spreader & heat sink due to itsexceptionally high thermal conductivity (>1000 W/mK). As shown in FIG.75, thermal dissipation is not uniform, rather it is concentrated in acertain part of the printed μ-LED. Thermal management strategy describedhere can be designed such that the heat sink is placed strategically onthe hot spot.

Placing a Heat Sink on Micro-Lens Used for Merging the Light Output fromthe Bi-Direction LED

A μ-LED printed onto a transparent substrate such as a glass or aplastic exhibits bi-axial illumination. Highly reflective metals (e.g.Al, Ag, Pt, and etc) can be deposited on the top of the printed μ-LED orμ-LED can be printed on highly reflective metal foil to reflect thelight to merge the light emission as discussed previously.

As illustrated in FIG. 78, a micro-lens can be fabricated or placed onthe printed μ-LED. These microlenses can simply be molded usingphoto-curable resin as illustrated in FIG. 78. Highly reflective andthermally conductive metals, such as Ag, can be plated, evaporated, orsputtered on top of the these structures to create a mirror-likestructures to reflect the light emitted from the printed μ-LED.Furthermore, these reflector can also be served as a heat sink due toits high thermal conductivity.

Example 15 Heterogeneous Integration of μ-LEDs with Printed Electronics

Utilizing step-and-repeat process, different classes of materials (i.e.μ-GaAs LEDs, μ-GaN LEDs, and printed μ-Si electronics, and etc) can beprinted in a sequence into a single substrate for combining advantagesof those different materials. For example, μ-Si is well suited fordeveloping a complex electronics based on its stable electronicproperties and matured processing technologies on both digital andanalog circuits. Instead of μ-Si, μ-GaAs chiplets or μ-GaN chipletscould be used as a building block for developing high-frequencyoperating analog circuits for Radio Frequency (RF) optoelectronics onunusual substrates such as a plastic. In FIG. 79, one example of combingμ-GaAs LED, μ-GaN LEDs, and μ-Si electronics for developing full-coloredinorganic active-matrix display is proposed.

Furthermore, carbon-based materials such as Carbon Nanotube (CNT) orGraphene films can be grown on another substrate and be transfer-printedonto already-printed μ-LEDs for developing a transparent electrodes andinterconnection (as an alternative to ITO or ZnO transparent electrodes)to prevent the interconnection lines from blocking the light output.Additionally, a photodiode can also be heterogeneously integrated ontothe printed μ-LEDs as illustrated in FIG. 80. A photodiode would simplydetect the light intensity from the printed μ-LED and the outputresponse of the photodiode can be fed back to the driving ICs for theμ-LEDs for the real-time self-calibration purpose.

Example 16 Integration of Phosphors and μ-GaN LEDs

White LED produced by combination of phosphor and a blue LED has severalchallenges to hurdle. One major challenge is the color uniformity. Dueto the lack of uniformity in phosphor coverage, the resulting emissionfrom the underlying blue LED and the phosphor varies considerably. As aresult, the edges appear to be yellow whereas the center of the beamappear to be blue. LUMILED has developed a patented process on conformalcoating of phosphor technology and thus far is the only LED manufacturerthat can produce white LED with high uniformity.

FIG. 81 illustrates a new technique to disperse phosphor particles inuniform and array-like fashion. As illustrated in FIG. 81, elastomer ismolded with an array of cavities. Geometries of these cavities caneasily be controlled by patterning the master substrate into thedesirable shapes and depths. Phosphor particles which have the diameterin the range of several microns can be mixed in the solvent, and pouredonto the elastomer. Phosphors on the surface of the elastomer can bescrapped away by the elastomer blade leaving phosphors only in thecavities. By bonding the thin elastomer onto the molded elastomer,phosphors can effectively be bound inside the cavities in array-likefashion. Packaged elastomer with encapsulated phosphors can be directlylaminated against the packaged μ-GaN LEDs on the flexible substrate asillustrated in FIG. 81(E). The distance between phosphors and LEDs andspacing between phosphor cells can be precisely controlled resulting inthe highest level of uniformity. 3D cartoons are shown in FIG. 82 andFIG. 83 for more clear illustrations. Micro-lens structures mentioned ina previous example can be incorporated as well simply by lamination.

Example 17 Methods for Making μ-LEDs

FIG. 84 illustrates an exemplary embodiment for making an array ofsemiconductor devices. A growth substrate 8401 is provided and asemiconductor epilayer 8402 is grown on the surface via epitaxialgrowth. The epilayer 8402 is bonded to a handle substrate 8403 and issubsequently released from the growth substrate 8401. Next, a mask 8404is patterned over the epilayer 8402 to define masked regions and exposedregions. Material is removed from the exposed regions to define thearray of semiconductor devices 8405. The semiconductor devices 8405 arepartially released from the handle substrate 8403, and remain connectedby anchors 8406. Optionally, the patterned mask is removed (not shown).The partially released semiconductor devices 8405 are subsequentlyselectively printed onto a device substrate via a contact printingmethod.

FIG. 85 illustrates an exemplary embodiment for making an array of GaNLED devices. A sapphire growth substrate 8501 is provided and a GaNmultilayer 8502 is grown on the surface via epitaxial growth. Themultilayer 8502 is bonded to a handle substrate 8503 and is subsequentlyreleased from the sapphire substrate 8501. Next, a mask 8504 ispatterned over the multilayer 8502 to define masked regions and exposedregions. Material is removed from the exposed regions to define thearray of GaN LED devices 8505. The GaN LED devices 8505 are partiallyreleased from the handle substrate 8503, and remain connected by anchors8506. Optionally, the patterned mask is removed (not shown). Thepartially released GaN LED devices 8505 are subsequently selectivelyprinted onto a device substrate via a contact printing method.

FIG. 86 illustrates an exemplary embodiment for making an array of GaNLED devices. A silicon (111) growth substrate 8601 is provided and a GaNmultilayer 8602 is grown on the surface via epitaxial growth. Next, amask 8603 is patterned over the multilayer 8602 to define masked regionsand exposed regions. Material is removed from the exposed regions todefine the array of GaN LED devices 8604. In this embodiment, a portionof the silicon substrate 8601 is removed from the exposed region by theetching process. The GaN LED devices 8604 are partially released fromthe silicon substrate 8601, for example by a direction etch along <110>directions of the silicon substrate 8601. In this embodiment, the GaNLED devices remain connected to the substrate by anchors 8605.Optionally, the patterned mask is removed (not shown). The partiallyreleased GaN LED devices 8604 are subsequently selectively printed ontoa device substrate via a contact printing method.

FIG. 87 illustrates an exemplary embodiment for making an array of GaNLED devices. A sapphire growth substrate 8701 is provided and asacrificial layer 8702 is deposited thereon. A GaN multilayer 8703 isgrown over the sacrificial layer 8602 via epitaxial growth. Next, a mask8704 is patterned over the multilayer 8703 to define masked regions andexposed regions. Material is removed from the exposed regions to definethe array of GaN LED devices 8705. The GaN LED devices 8505 arepartially released from the sapphire substrate 8701 by etching portionsof the sacrificial layer. In this embodiment, the GaN LED devices remainconnected to the substrate by anchors 8706. Optionally, the patternedmask is removed (not shown). The partially released GaN LED devices 8705are subsequently selectively printed onto a device substrate via acontact printing method.

FIG. 88 illustrates an exemplary embodiment for making an array ofsemiconductor devices. A sapphire growth substrate 8801 is provided anda GaN multilayer 8802 is grown on the surface via epitaxial growth. TheGaN multilayer 8802 is bonded to a handle substrate 8803. To release theGaN multilayer 8802 from the sapphire substrate 8801, the interface 8805between the sapphire substrate 8801 and the GaN multilayer 8802 isexposed to laser radiation 8804, thereby releasing the GaN multilayer8802 from the sapphire substrate 8801. Next, a mask 8806 is patternedover the GaN multilayer 8802 to define masked regions and exposedregions. Material is removed from the exposed regions to define thearray of GaN LEDs 8807. The GaN LED devices 8807 are partially releasedfrom the handle substrate 8803, and remain connected by anchors 8808.Optionally, the patterned mask is removed (not shown). The partiallyreleased semiconductor devices 8808 are subsequently selectively printedonto a device substrate via a contact printing method (not shown).

Example 18 Handle Substrate Processing

In some embodiments, a handle substrate is useful as an intermediateprocessing platform. For example, devices transferred to a handlesubstrate may undergo one or more patterning, growth, polishing,deposition, implantation, etching, annealing or other processing steps.Processing of electronic devices on a handle substrate may be useful,for example, if the handle substrate is capable of withstanding hightemperatures or chemically inert. Such advantages are furtheradvantageous if the growth and/or device substrates are, for example,not capable of withstanding high temperatures or not chemically inert. Ahandle substrate may also be useful, for example, as an assembly stage,where multiple electronic device components are positioned relative toone another to reduce the number of overall process steps and/or tolimit processing steps on a device or growth substrate.

FIG. 89 illustrates a scheme for processing electronic devices on ahandle substrate. In this embodiment, electronic devices 8901 are grownand patterned on a growth substrate 8902. At least a portion of theelectronic devices 8901 are transferred to a handle substrate 8903, forexample using methods described above, where they undergo additionalprocessing. In this embodiment, handle substrate is capable ofwithstanding high temperature processing, for example for patterningohmic contacts 8904 onto electronic devices 8901. After electronicdevices 8901 are patterned with ohmic contacts 8904, they aretransferred to a device substrate 8905 via a contact printing method.Additional processing of electronic devices 8901 while on the handlesubstrate 8903 is further contemplated.

FIGS. 90A and 90B illustrates another scheme for processing electronicdevices on a handle substrate. In this embodiment, multilayer devices9001 are grown on a growth substrate 9002. The multilayer device 9001shown in FIG. 90A comprises a seed/buffer layer 9003 separating a loweractive device layer(s) 9004 from the growth substrate 9002. Asacrificial layer 9005 separates the lower active device layer(s) 9004from an upper active device layer(s) 9006. FIG. 90B illustrates a usefultransfer scheme for such multilayer devices 9001 via transfer to handlesubstrates 9007 and 9008. The prepared multilayer devices 9001 are firstprocessed to transfer upper active device layers 9006 to a first handlesubstrate 9007, for example by at least partially removing sacrificiallayers 9005 followed by a transfer step. Lower active device layers 9004are then left exposed and still attached to growth substrate 9002, afterwhich they are transferred to a second handle substrate 9008, forexample using methods described above.

FIG. 91 illustrates another scheme for processing electronic devices ona handle substrate. In this embodiment, electronic devices 9101 and 9102are prepared on separate growth substrates 9103 and 9104, respectively.After growth and any necessary processing on the growth substrate (notshown), portions of each of the electronic devices 9101 and 9102 aretransferred to a handle substrate 9105. Methods such as these allow forheterogeneously integrated electronic devices in a lateral configurationto be assembled onto a handle substrate. Optionally, electronic devices9101 and 9102 undergo additional processing while on handle substrate9105 before transfer to an appropriate device substrate (not shown). Inone embodiment, electronic devices 9101 are first transferred to handlesubstrate 9105 followed by transfer of electronic devices 9102 to handlesubstrate 9105. In an embodiment, electronic devices 9101 and 9102 aretransferred to handle substrate 9105 in a step-wise fashion, where oneor more of electronic devices 9101 are transferred to handle substrate9105 in one step, followed by transfer of one or more electronic devices9102 to handle substrate 9105 in another step; additional transfer stepsfor electronic devices 9101 and 9102 are further contemplated, as aretransfer of additional electronic devices to handle substrate 9105.

Alternative to or in addition to lateral configuration, devices can beheterogeneously integrated in a vertical configuration. Such a schemefor processing is shown in FIGS. 92A and 92B. In this embodiment, twodifferent light emitting diode devices 9201 and 9202 are prepared on twodifferent growth substrates, 9203 and 9204, respectively. At least aportion of light emitting diode devices 9201 are first transferred to ahandle substrate 9205. At least a portion of light emitting diodedevices 9202 are subsequently transferred to handle substrate 9205 ontop of light emitting diode devices 9201. Optionally, intermediateprocessing of light emitting diode devices 9201 take place beforetransfer of light emitting diode devices 9202. FIG. 92B illustrates across sectional view of the vertically configured heterogeneouslyintegrated devices on handle substrate 9205. Optionally, additionaldevices are further vertically integrated on handle substrate 9205. In aspecific embodiment, light emitting diode devices 9201 emit blue lightand light emitting diode devices 9202 emit red light.

FIG. 93 shows another example of processing an electronic device on ahandle substrate. In this embodiment, buffer layer 9301 and electronicdevice 9302 are grown and optionally pre-processed on growth substrate9303. In this specific embodiment, electronic device 9302 is a verticaltype LED comprising n-type GaN region 9304, quantum well region 9305 andp-type GaN region 9306. Buffer layer 9301 and electronic device 9302 aredetached from growth substrate 9303 and transferred to handle substrate9307, for example using methods described above. While on handlesubstrate 9307, buffer layer 9301 is removed and, optionally, a portionof electronic device 9302 is also removed. Buffer layer 9301 andportions of electronic device 9302 are optionally removed by methodsknown in the art, such as chemical-mechanical polishing (CMP). Thepolished devices 9308 may subsequently be transferred to a devicesubstrate and/or undergo additional processing while on the handlesubstrate (not shown).

FIG. 94 shows another example of processing an electronic device on ahandle substrate. In this embodiment, electronic devices 9401 are grownand optionally patterned on a growth substrate 9402. At least a portionof the electronic devices 9401 are transferred to a handle substrate9403, for example using methods described above. Here, heat managementstructures 9404 are patterned over the electronic devices 9401 on thehandle substrate 9403. After patterning of heat management structures9404, at least a portion of electronic devices 9401 and heat managementstructures 9404 are transferred to a device substrate 9405, for examplevia a contact printing method. In specific embodiments, patterning ofheat management structures 9404 is a high temperature process and handlesubstrate 9403 is capable of withstanding the associated processingconditions with would otherwise damage or destroy growth substrate 9402or device substrate 9405.

STATEMENTS REGARDING INCORPORATION BY REFERENCE AND VARIATIONS

All references throughout this application, for example patent documentsincluding issued or granted patents or equivalents; patent applicationpublications; and non-patent literature documents or other sourcematerial; are hereby incorporated by reference herein in theirentireties, as though individually incorporated by reference, to theextent each reference is at least partially not inconsistent with thedisclosure in this application (for example, a reference that ispartially inconsistent is incorporated by reference except for thepartially inconsistent portion of the reference).

The terms and expressions which have been employed herein are used asterms of description and not of limitation, and there is no intention inthe use of such terms and expressions of excluding any equivalents ofthe features shown and described or portions thereof, but it isrecognized that various modifications are possible within the scope ofthe invention claimed. Thus, it should be understood that although thepresent invention has been specifically disclosed by preferredembodiments, exemplary embodiments and optional features, modificationand variation of the concepts herein disclosed may be resorted to bythose skilled in the art, and that such modifications and variations areconsidered to be within the scope of this invention as defined by theappended claims. The specific embodiments provided herein are examplesof useful embodiments of the present invention and it will be apparentto one skilled in the art that the present invention may be carried outusing a large number of variations of the devices, device components,methods steps set forth in the present description. As will be obviousto one of skill in the art, methods and devices useful for the presentmethods can include a large number of optional composition andprocessing elements and steps.

When a group of substituents is disclosed herein, it is understood thatall individual members of that group and all subgroups are disclosedseparately. When a Markush group or other grouping is used herein, allindividual members of the group and all combinations and subcombinationspossible of the group are intended to be individually included in thedisclosure. Specific names of compounds or materials are intended to beexemplary, as it is known that one of ordinary skill in the art can namethe same compounds or materials differently.

Every formulation or combination of components described or exemplifiedherein can be used to practice the invention, unless otherwise stated.

Whenever a range is given in the specification, for example, atemperature range, a time range, or a composition or concentrationrange, all intermediate ranges and subranges, as well as all individualvalues included in the ranges given are intended to be included in thedisclosure. It will be understood that any subranges or individualvalues in a range or subrange that are included in the descriptionherein can be excluded from the claims herein.

All patents and publications mentioned in the specification areindicative of the levels of skill of those skilled in the art to whichthe invention pertains. References cited herein are incorporated byreference herein in their entirety to indicate the state of the art asof their publication or filing date and it is intended that thisinformation can be employed herein, if needed, to exclude specificembodiments that are in the prior art. For example, when composition ofmatter are claimed, it should be understood that compounds known andavailable in the art prior to Applicant's invention, including compoundsfor which an enabling disclosure is provided in the references citedherein, are not intended to be included in the composition of matterclaims herein.

As used herein, “comprising” is synonymous with “including,”“containing,” or “characterized by,” and is inclusive or open-ended anddoes not exclude additional, unrecited elements or method steps. As usedherein, “consisting of” excludes any element, step, or ingredient notspecified in the claim element. As used herein, “consisting essentiallyof” does not exclude materials or steps that do not materially affectthe basic and novel characteristics of the claim. In each instanceherein any of the terms “comprising”, “consisting essentially of” and“consisting of” may be replaced with either of the other two terms. Theinvention illustratively described herein suitably may be practiced inthe absence of any element or elements, limitation or limitations whichis not specifically disclosed herein.

One of ordinary skill in the art will appreciate that startingmaterials, reagents, synthetic methods, purification methods, analyticalmethods, assay methods and methods other than those specificallyexemplified can be employed in the practice of the invention withoutresort to undue experimentation. All art-known functional equivalents,of any such materials and methods are intended to be included in thisinvention. The terms and expressions which have been employed are usedas terms of description and not of limitation, and there is no intentionthat in the use of such terms and expressions of excluding anyequivalents of the features shown and described or portions thereof, butit is recognized that various modifications are possible within thescope of the invention claimed. Thus, it should be understood thatalthough the present invention has been specifically disclosed bypreferred embodiments and optional features, modification and variationof the concepts herein disclosed may be resorted to by those skilled inthe art, and that such modifications and variations are considered to bewithin the scope of this invention as defined by the appended claims.

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1. (canceled)
 2. A method of making an electronic device, the methodcomprising the steps of: providing a growth substrate having a receivingsurface; forming a semiconductor epilayer on said receiving surface viaepitaxial growth, said semiconductor epilayer having a first contactsurface; bonding said first contact surface of said semiconductorepilayer to a handle substrate; releasing said semiconductor epilayerfrom said growth substrate, wherein at least a portion of saidsemiconductor epilayer remains bonded to said handle substrate, therebyexposing a second contact surface of said semiconductor epilayer;processing said semiconductor epilayer on said handle substrate, therebygenerating one or more semiconductor structures supported by said handlesubstrate; transferring at least one of said one or more semiconductorstructures from said handle substrate to a device substrate via drytransfer contact printing, thereby assembling said semiconductorstructures on said device substrate to make said electronic device.
 3. Amethod of making an electronic device, the method comprising the stepsof: providing a first growth substrate having a first receiving surface;forming a first semiconductor epilayer on said first receiving surfacevia epitaxial growth, said first semiconductor epilayer having a firstcontact surface; bonding said first contact surface of said firstsemiconductor epilayer to a handle substrate; releasing said firstsemiconductor epilayer from said first growth substrate, wherein atleast a portion of said first semiconductor epilayer remains bonded tosaid handle substrate, thereby exposing a second contact surface of saidfirst semiconductor epilayer; providing a second growth substrate havinga second receiving surface; forming a second semiconductor epilayer onsaid second receiving surface via epitaxial growth; said secondsemiconductor epilayer having a third contact surface; bonding saidthird contact surface of said second semiconductor epilayer to saidhandle substrate, said first semiconductor epilayer or both; releasingsaid second semiconductor epilayer from said second growth substrate,wherein at least a portion of said second semiconductor epilayer remainsbonded to said handle substrate, said first semiconductor epilayer orboth, thereby exposing a fourth contact surface of said secondsemiconductor epilayer; processing said first semiconductor epilayer,said second semiconductor epilayer or both said first and said secondsemiconductor epilayers on said handle substrate, thereby generating oneor more semiconductor structures supported by said handle substrate;transferring at least one of said one or more semiconductor structuresfrom said handle substrate to a device substrate via dry transfercontact printing, thereby assembling said semiconductor structures onsaid device substrate to make said electronic device.
 4. The method ofclaim 2, wherein said step of processing a semiconductor epilayer onsaid handle substrate comprises a processing method selected from thegroup consisting of: a patterning process, a growth process, a polishingprocess, a deposition process, an implantation process, an etchingprocess, an annealing process, a molding process, a curing process, acoating process and any combination of these.
 5. The method of claim 2,wherein said step of processing a semiconductor epilayer on said handlesubstrate comprises forming one or more ohmic contacts on saidsemiconductor epilayer.
 6. The method of claim 2, wherein said step ofprocessing a semiconductor epilayer on said handle substrate comprisesforming one or more thermal management structures on said semiconductorepilayer. 7-37. (canceled)
 38. The method of claim 2, further comprisinga step of processing said semiconductor epilayer on said growthsubstrate.
 39. The method of claim 38, wherein said step of processingsaid semiconductor epilayer on said handle substrate comprises aprocessing method selected from the group consisting of: a patterningprocess, a growth process, a polishing process, a deposition process, animplantation process, an etching process, an annealing process, amolding process, a curing process, a coating process and any combinationof these. 40-97. (canceled)
 98. A method of making a semiconductordevice, the method comprising the steps of: providing a transparentsubstrate; assembling a semiconductor device on a surface of saidtransparent substrate via dry transfer contact printing; providing oneor more metallic contacts in electrical contact with said semiconductordevice; coating said semiconductor device and one or more metalliccontacts with a photosensitive polymer layer; exposing portions of saidphotosensitive polymer layer to electromagnetic radiation, wherein saidelectromagnetic radiation is at least partially transmitted through saidtransparent substrate and wherein said one or more metallic contactsblock at least a portion of said electromagnetic radiation from reachingat least a portion of said photosensitive polymer layer, said one ormore metallic contacts thereby serving as one or more self-aligned maskelements.
 99. The method of claim 98, further comprising a step ofremoving portions of said photosensitive polymer layer which are maskedby said one or more metallic contacts serving as self-aligned maskelements.
 100. The method of claim 99, wherein said step of removingportions of said photosensitive polymer layer which are masked by saidone or more metallic contacts serving as self-aligned mask elementscomprises developing said photosensitive polymer layer and whereinregions of the photosensitive polymer layer that were not exposed tosaid electromagnetic radiation are dissolved by exposure to a solvent.101. The method claim 98, wherein said transparent substrate comprises amaterial selected from the group consisting of: glass, quartz, sapphire,PET, mylar, PDMS, kapton, polycarbonate, silicone, polyurethane,ethylene tetrafluoroethylene, diamond and any combination of these. 102.The method of claim 98, wherein said electromagnetic radiation haswavelengths selected over the range of 100 nm to 800 nm.
 103. The methodof claim 98, wherein said semiconductor device transmits at least 1% ofsaid electromagnetic radiation.
 104. The method of claim 98, wherein atleast a portion of said electromagnetic radiation provided to saidtransparent substrate is reflected, scattered or absorbed by said one ormore metallic contacts.
 105. The method of claim 98, wherein at least50% of said electromagnetic radiation received by said one or moremetallic contacts is reflected, scattered or absorbed by said one ormore metallic contacts.
 106. The method of claim 98, wherein at least75% of said electromagnetic radiation received by said one or moremetallic contacts is reflected, scattered or absorbed by said one ormore metallic contacts.
 107. The method of claim 98, wherein at least95% of said electromagnetic radiation received by said one or moremetallic contacts is reflected, scattered or absorbed by said one ormore metallic contacts.
 108. The method of claim 98, wherein each ofsaid one or more metallic contacts comprises a material selected fromthe group consisting of: gold, nickel, copper, palladium, platinum,silver, titanium, aluminum, molybdenum and any combination of these.109. The method of claim 98, wherein each of said one or more metalliccontacts has a thickness selected over the range of 4 nm to 10 μm. 110.The method of claim 98, wherein said photosensitive polymer layer has athickness selected from the range of 5 nm to 1 mm.
 111. The method ofclaim 98, wherein said photosensitive polymer is a negative tonephotopolymer.
 112. The method of claim 98, wherein portions of saidphotosensitive polymer exposed to electromagnetic radiation are at leastpartially crosslinked.
 113. The method of claim 98, wherein saidphotosensitive polymer comprises a material selected from the groupconsisting of: BCB, SUB, WL-5351, polyurethane, silicon, spin-on-glass,polyimide and any combination of these.
 114. The method of claim 98,wherein said semiconductor device comprises a LED, a P-N junction, athin film transistor, a single junction solar cell, a multi-junctionsolar cell, a photodiode, a laser, a sensor, a photodiode, anelectro-optical device, a CMOS device, a MOSFET device, a MESFET device,a photovoltaic cell, a microelectromechanical device, ananoelectromechanical device, a HEMT device, a light-emitting transistoror any combination of these.
 115. A method for making an array ofphosphors, said method comprising the steps of: molding an elastomerlayer with an array of recessed regions; providing phosphor particlesover said elastomer layer, wherein said phosphor particles at leastpartially fill in said array of recessed regions; and providing anencapsulation layer over said elastomer layer, wherein said phosphorparticles are encapsulated in said array of recessed regions, therebymaking said array of phosphors.
 116. A method for making a packagedarray of LEDs, said method comprising the steps of: molding an elastomerlayer with an array of recessed regions; providing phosphor particlesover said elastomer layer, wherein said phosphor particles at leastpartially fill in said array of recessed regions; providing anencapsulation layer over said elastomer layer, wherein said phosphorparticles are encapsulated in said array of recessed regions, therebymaking an array of phosphors; and laminating said array of phosphorsover an array of LED device structures, thereby making said packagedarray of LEDs.
 117. The method of claim 115, wherein said recessedregions have depths selected over the range of 5 nm to 10 mm.
 118. Themethod of claim 116, further comprising a step of making said array ofLED device structures.
 119. The method of claim 118, wherein said stepof making said array of LED device structures comprises the steps of:providing a sapphire growth substrate having a receiving surface;forming a GaN epilayer on said receiving surface via epitaxial growth;wherein said GaN epilayer is a multilayer comprising at least onep-doped GaN semiconductor layer in electrical contact with at least onen-doped GaN semiconductor layer, said GaN multilayer having a firstcontact surface; bonding said first contact surface of said GaNmultilayer to a handle substrate; releasing said GaN multilayer fromsaid growth substrate, wherein said GaN multilayer remains bonded tosaid handle substrate, thereby exposing a second contact surface of saidGaN multilayer; patterning said second contact surface of said GaNmultilayer with a mask, thereby generating exposed regions and one ormore masked regions of said second contact surface; removing materialfrom said exposed regions by etching said exposed regions, therebygenerating one or more LED device structures supported by said handlesubstrate; at least partially releasing said one or more LED devicestructures from said handle substrate; and transferring at least aportion of said one or more LED device structures from said handlesubstrate to a device substrate via dry transfer contact printing,thereby making said array of LEDs.
 120. The method of claim 116, whereinsaid step of laminating comprises printing said array of phosphors ontoa device substrate comprising an array of LED device structures.
 121. Amethod of making an electronic device, said method comprising the stepsof: providing one or more electronic device components; contacting saidone or more electronic device components with a conformal transfer andmolding device, thereby transferring said one or more electronic devicecomponents onto said conformal transfer and molding device; contacting aprepolymer layer disposed over a host substrate with said conformaltransfer and molding device having said one or more electronic devicecomponents positioned thereon, thereby at least partially embedding saidone or more electronic device components into said prepolymer layer andpatterning said prepolymer layer with one or more recessed features;curing said prepolymer layer, thereby forming a polymer layer having oneor more recessed features; and filling at least a portion of said one ormore recessed features with a filling material selected from the groupconsisting of: a conductive material, an optical material, a heattransfer material and any combination of these.
 122. The method of claim121, wherein said filling step comprises the steps of: providing afilling material on a surface of said polymer; and dragging a scrapingtool along said surface of said polymer to fill said filling materialinto at least a portion of said one or more recessed features.
 123. Themethod of claim 121, wherein said host substrate comprises a materialselected from the group consisting of: polymer, glass, plastic,semiconductor, sapphire, ceramic and any combination of these.
 124. Themethod of claim 121, wherein said prepolymer layer comprises a materialselected from the group consisting of: a photocurable polymer, athermally curable polymer, a photocurable polyurethane, SU8, PDMS, NOAseries, photosensitive polyimide, photosensitive silicone and anycombination of these.
 125. The method of claim 121, wherein said step ofcuring said prepolymer layer comprises exposing said prepolymer layer toelectromagnetic radiation or heating said prepolymer layer.
 126. Themethod of claim 121, further comprising a step of curing said fillingmaterial.
 127. The method of claim 126, wherein said step of curing saidfilling material comprises heating said filling material or exposingsaid filling material to electromagnetic radiation.
 128. The method ofclaim 121, wherein at least one of said one or more electronic devicecomponents comprises one or more electrode contacts.
 129. The method ofclaim 128, further comprising a step of etching at least a portion ofsaid polymer to expose said one or more electrode contacts.
 130. Themethod of claim 121, wherein said filling material comprises aconductive material.
 131. The method of claim 130, wherein saidconductive material provides one or more electrical interconnections toat least one electronic device component.
 132. The method of claim 130,wherein said conductive material is in electrical communication with oneor more electrode contacts of said one or more electronic devicecomponents.
 133. The method of claim 130, wherein, after curing, saidconductive material has a resistivity selected over the range of 1×10-10to 1×10-2 Ω·cm.
 134. The method of claim 130, wherein said conductivematerial comprises a conductive paste selected from the group consistingof: silver epoxy, gold epoxy, copper epoxy, aluminum epoxy and anycombination of these.
 135. The method of claim 121, wherein said fillingmaterial comprises an optical material.
 136. The method of claim 135,wherein said optical material forms an optical element selected from thegroup consisting of: a collecting optic, a concentrating optic, areflective optic, a diffusing optic, a dispersive optic, a lens, aphosphor, a waveguide, an optical fiber, an optical coating, atransparent optic, an optical filter, a polarizing optic and anycombination of these.
 137. The method of claim 135, wherein said opticalmaterial comprises a material selected from the group consisting of:polymer, plastic, glass, phosphor and any combination of these.
 138. Themethod of claim 121, wherein at least one of said one or more electronicdevice components is selected from the group consisting of: a P-Njunction, a thin film transistor, a single junction solar cell, amulti-junction solar cell, a photodiode, a light emitting diode, alaser, a sensor, a photodiode, an electro-optical device, a CMOS device,a MOSFET device, a MESFET device, a photovoltaic cell, amicroelectromechanical device, a HEMT device and any combination ofthese.
 139. The method of claim 121, wherein at least one of said one ormore electronic device components has a vertical dimension selected overthe range of 10 nm to 10 μm.
 140. The method of claim 121, wherein atleast one of said one or more electronic device components has a lateraldimension selected over the range of 1 μm to 10 mm.
 141. A method ofmaking an electronic device, said method comprising the steps of:providing a conformal transfer and molding device having a contactsurface comprising one or more transfer surfaces and one or more raisedmolding features; contacting one or more electronic device componentswith said conformal transfer and molding device, thereby positioningsaid one or more electronic device components on said one or moretransfer surfaces of said conformal transfer and molding device;contacting a prepolymer layer disposed over a host substrate with saidconformal transfer and molding device having said one or more electronicdevice components positioned thereon, thereby at least partiallyembedding said one or more electronic device components and said one ormore raised molding features into said prepolymer layer; curing saidprepolymer layer, thereby forming a polymer layer, wherein said one ormore raised molding features of said conformal transfer and moldingdevice are replicated as one or more recessed features in said polymerlayer; separating said conformal transfer and molding device from saidpolymer layer, wherein said one or more electronic device components areretained in said polymer layer; applying a filling material to a surfaceof said polymer layer; and dragging a scraping tool along said surfaceof said polymer to fill said filling material into at least a portion ofsaid one or more recessed features.
 142. The method of claim 141,wherein said filling material is selected from the group consisting of:a conductive material, an optical material, a heat transfer material andany combination of these.
 143. A method of making an electronic device,said method comprising the steps of: providing a host substrate with aprepolymer disposed thereon; at least partially embedding one or moreelectronic device components into said prepolymer layer, wherein one ormore recessed features are patterned in said prepolymer layer duringsaid embedding step; curing said prepolymer layer, thereby forming apolymer layer having one or more recessed features and fixing said oneor more electronic device components in said polymer layer; and fillingat least a portion of said one or more recessed features with aconductive material, wherein said conductive material provides one ormore electrical interconnections to at least one electronic devicecomponent.
 144. A method for making a printable electronic device on adevice substrate, said method comprising the steps of: providing aprintable electronic device having a contact area, wherein saidprintable electronic device is anchored to a host substrate via one ormore homogeneous or heterogeneous anchors; contacting said contact areaof said printable electronic device with a contact surface of aconformable transfer device, wherein said contact surface of saidconformable transfer device has an area smaller than said contact areaof said printable electronic device, and wherein said contact area andsaid contact surface are aligned off center from each other, whereincontact between said contact surface and said contact area binds saidprintable electronic device to said contact surface; separating saidprintable electronic device and said host substrate, thereby releasingsaid one or more homogeneous or heterogeneous anchors; contacting saidprintable electronic device disposed on said contact surface with areceiving surface of said device substrate; and separating said contactsurface of said conformable transfer device and said printableelectronic device, wherein said printable electronic device istransferred onto said receiving surface, thereby assembling saidprintable electronic device on said receiving surface of said devicesubstrate.
 145. The method of claim 144, wherein said contact surface ofsaid conformable transfer device is less than 50% of said contact areaof said electronic device.
 146. The method of claim 144, wherein saidcontact surface of said conformable transfer device is 25% to 75% ofsaid contact area of said electronic device.
 147. The method of claim144, wherein said contact area and said contact surface are aligned offcenter from each other by at least 1 μm.
 148. The method of claim 144,wherein said contact area and said contact surface are aligned offcenter from each other by 1 μm to 100 μm.
 149. The method of claim 144,wherein said contact surface is provided on a relief feature of saidconformable transfer device.
 150. The method of claim 144, wherein saidconformable transfer device comprises a plurality of relief featuresproviding a plurality of contact regions; said method comprising:providing a plurality of printable electronic devices each having acontact area, wherein each of said printable electronic devices isanchored to a host substrate via one or more homogeneous orheterogeneous anchors; contacting said contact areas of said printableelectronic devices with said contact regions of said conformabletransfer device, wherein each of said contact regions of saidconformable transfer device has an area smaller than said each ofcontact areas of said printable electronic device, and wherein saidcontact areas and said contact regions are aligned off center from eachother, wherein contact between said contact regions and said contactareas binds said printable electronic devices to said contact regions;separating said printable electronic devices and said host substrate,thereby releasing said homogeneous or heterogeneous anchors; contactingsaid printable electronic devices disposed on said contact regions witha receiving surface of said device substrate; and separating saidcontact surfaces of said conformable transfer device and said printableelectronic devices, wherein said printable electronic devices aretransferred onto said receiving surface, thereby assembling saidprintable electronic devices on said receiving surface of said devicesubstrate.
 151. The method of claim 144, wherein said conformabletransfer device is a PDMS stamp.
 152. The method of claim 144, whereinsaid electronic device is a P-N junction, a thin film transistor, asingle junction solar cell, a multi-junction solar cell, a photodiode, alight emitting diode, a laser, a CMOS device, a MOSFET device, a MESFETdevice, a photovoltaic cell, a microelectromechanical device, a HEMTdevice or any combination of these.
 153. The method of claim 144,wherein said device substrate is a glass substrate, a polymer substrate,a semiconductor substrate, a metal substrate or a ceramic substrate.154. The method of claim 144, wherein said device substrate is aflexible substrate, a large area substrate, a pre-metalized substrate, asubstrate pre-patterned with one or more device components, or anycombination of these. 155-201. (canceled)